summaryrefslogtreecommitdiffstats
path: root/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
diff options
context:
space:
mode:
authorUlrich Weigand <ulrich.weigand@de.ibm.com>2013-03-19 19:50:30 +0000
committerUlrich Weigand <ulrich.weigand@de.ibm.com>2013-03-19 19:50:30 +0000
commitfd24544ff860b056544fbc6590fe09538b03e4f8 (patch)
treef42b213c3ebc49467e0d495fef74e550fdff9846 /llvm/lib/Target/PowerPC/PPCInstr64Bit.td
parent80d9ad398db1e834d78bb8700e7409e418fcd329 (diff)
downloadbcm5719-llvm-fd24544ff860b056544fbc6590fe09538b03e4f8.tar.gz
bcm5719-llvm-fd24544ff860b056544fbc6590fe09538b03e4f8.zip
Fix sub-operand size mismatch in tocentry operands.
The tocentry operand class refers to 64-bit values (it is only used in 64-bit, where iPTR is a 64-bit type), but its sole suboperand is designated as 32-bit type. This causes a mismatch to be detected at compile-time with the TableGen patch I'll check in shortly. To fix this, this commit changes the suboperand to a 64-bit type as well. llvm-svn: 177427
Diffstat (limited to 'llvm/lib/Target/PowerPC/PPCInstr64Bit.td')
-rw-r--r--llvm/lib/Target/PowerPC/PPCInstr64Bit.td2
1 files changed, 1 insertions, 1 deletions
diff --git a/llvm/lib/Target/PowerPC/PPCInstr64Bit.td b/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
index 429a9216205..c2fdba13d1f 100644
--- a/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
+++ b/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
@@ -30,7 +30,7 @@ def symbolLo64 : Operand<i64> {
let EncoderMethod = "getLO16Encoding";
}
def tocentry : Operand<iPTR> {
- let MIOperandInfo = (ops i32imm:$imm);
+ let MIOperandInfo = (ops i64imm:$imm);
}
def memrs : Operand<iPTR> { // memri where the immediate is a symbolLo64
let PrintMethod = "printMemRegImm";
OpenPOWER on IntegriCloud