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authorNemanja Ivanovic <nemanja.i.ibm@gmail.com>2015-04-11 10:40:42 +0000
committerNemanja Ivanovic <nemanja.i.ibm@gmail.com>2015-04-11 10:40:42 +0000
commitc38b5311cbfa97b92ec9bd0936e99b85af46b95f (patch)
tree030b1d87db024d4b2665002cb46861a9510a50af /llvm/lib/Target/PowerPC/PPCISelLowering.h
parent87638f6345a931dd0a9d8c5fb35089593b1cc4f9 (diff)
downloadbcm5719-llvm-c38b5311cbfa97b92ec9bd0936e99b85af46b95f.tar.gz
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Add direct moves to/from VSR and exploit them for FP/INT conversions
This patch corresponds to review: http://reviews.llvm.org/D8928 It adds direct move instructions to/from VSX registers to GPR's. These are exploited for FP <-> INT conversions. llvm-svn: 234682
Diffstat (limited to 'llvm/lib/Target/PowerPC/PPCISelLowering.h')
-rw-r--r--llvm/lib/Target/PowerPC/PPCISelLowering.h13
1 files changed, 13 insertions, 0 deletions
diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.h b/llvm/lib/Target/PowerPC/PPCISelLowering.h
index 695fc3ff5bb..7e2ebd40d42 100644
--- a/llvm/lib/Target/PowerPC/PPCISelLowering.h
+++ b/llvm/lib/Target/PowerPC/PPCISelLowering.h
@@ -119,6 +119,15 @@ namespace llvm {
/// resultant GPR. Bits corresponding to other CR regs are undefined.
MFOCRF,
+ /// Direct move from a VSX register to a GPR
+ MFVSR,
+
+ /// Direct move from a GPR to a VSX register (algebraic)
+ MTVSRA,
+
+ /// Direct move from a GPR to a VSX register (zero)
+ MTVSRZ,
+
// FIXME: Remove these once the ANDI glue bug is fixed:
/// i1 = ANDIo_1_[EQ|GT]_BIT(i32 or i64 x) - Represents the result of the
/// eq or gt bit of CR0 after executing andi. x, 1. This is used to
@@ -645,6 +654,10 @@ namespace llvm {
void LowerFP_TO_INTForReuse(SDValue Op, ReuseLoadInfo &RLI,
SelectionDAG &DAG, SDLoc dl) const;
+ SDValue LowerFP_TO_INTDirectMove(SDValue Op, SelectionDAG &DAG,
+ SDLoc dl) const;
+ SDValue LowerINT_TO_FPDirectMove(SDValue Op, SelectionDAG &DAG,
+ SDLoc dl) const;
SDValue getFramePointerFrameIndex(SelectionDAG & DAG) const;
SDValue getReturnAddrFrameIndex(SelectionDAG & DAG) const;
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