Refactor all the addressing mode selection stuff into the isel lowering

class, where it can be used for preinc formation.

llvm-svn: 31536

1 files changed, 33 insertions, 1 deletions

diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.h b/llvm/lib/Target/PowerPC/PPCISelLowering.h
index 2d4ec1d3d7a..87b938a0759 100644
--- a/llvm/lib/Target/PowerPC/PPCISelLowering.h
+++ b/llvm/lib/Target/PowerPC/PPCISelLowering.h
@@ -176,13 +176,45 @@ namespace llvm {
     /// getTargetNodeName() - This method returns the name of a target specific
     /// DAG node.
     virtual const char *getTargetNodeName(unsigned Opcode) const;
+
+    /// getPreIndexedAddressParts - returns true by value, base pointer and
+    /// offset pointer and addressing mode by reference if the node's address
+    /// can be legally represented as pre-indexed load / store address.
+    virtual bool getPreIndexedAddressParts(SDNode *N, SDOperand &Base,
+                                           SDOperand &Offset,
+                                           ISD::MemOpAddrMode &AM,
+                                           SelectionDAG &DAG);
+    
+    /// SelectAddressRegReg - Given the specified addressed, check to see if it
+    /// can be represented as an indexed [r+r] operation.  Returns false if it
+    /// can be more efficiently represented with [r+imm].
+    bool SelectAddressRegReg(SDOperand N, SDOperand &Base, SDOperand &Index,
+                             SelectionDAG &DAG);
+    
+    /// SelectAddressRegImm - Returns true if the address N can be represented
+    /// by a base register plus a signed 16-bit displacement [r+imm], and if it
+    /// is not better represented as reg+reg.
+    bool SelectAddressRegImm(SDOperand N, SDOperand &Disp, SDOperand &Base,
+                             SelectionDAG &DAG);
+    
+    /// SelectAddressRegRegOnly - Given the specified addressed, force it to be
+    /// represented as an indexed [r+r] operation.
+    bool SelectAddressRegRegOnly(SDOperand N, SDOperand &Base, SDOperand &Index,
+                                 SelectionDAG &DAG);
+
+    /// SelectAddressRegImmShift - Returns true if the address N can be
+    /// represented by a base register plus a signed 14-bit displacement
+    /// [r+imm*4].  Suitable for use by STD and friends.
+    bool SelectAddressRegImmShift(SDOperand N, SDOperand &Disp, SDOperand &Base,
+                                  SelectionDAG &DAG);
+
     
     /// LowerOperation - Provide custom lowering hooks for some operations.
     ///
     virtual SDOperand LowerOperation(SDOperand Op, SelectionDAG &DAG);
     
     virtual SDOperand PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
-
+    
     virtual void computeMaskedBitsForTargetNode(const SDOperand Op,
                                                 uint64_t Mask,
                                                 uint64_t &KnownZero,