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authorMichael Liao <michael.liao@intel.com>2013-03-01 18:40:30 +0000
committerMichael Liao <michael.liao@intel.com>2013-03-01 18:40:30 +0000
commit6af16fc3b7d0355ca43b838ef79faaa63c44b6b5 (patch)
tree4ba86621fb61c4e2323158ec1261600f9cd91344 /llvm/lib/Target/PowerPC/PPCISelLowering.h
parent9660343b423ecce2cac5b125f87d145bb3cd12b4 (diff)
downloadbcm5719-llvm-6af16fc3b7d0355ca43b838ef79faaa63c44b6b5.tar.gz
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Fix PR10475
- ISD::SHL/SRL/SRA must have either both scalar or both vector operands but TLI.getShiftAmountTy() so far only return scalar type. As a result, backend logic assuming that breaks. - Rename the original TLI.getShiftAmountTy() to TLI.getScalarShiftAmountTy() and re-define TLI.getShiftAmountTy() to return target-specificed scalar type or the same vector type as the 1st operand. - Fix most TICG logic assuming TLI.getShiftAmountTy() a simple scalar type. llvm-svn: 176364
Diffstat (limited to 'llvm/lib/Target/PowerPC/PPCISelLowering.h')
-rw-r--r--llvm/lib/Target/PowerPC/PPCISelLowering.h2
1 files changed, 1 insertions, 1 deletions
diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.h b/llvm/lib/Target/PowerPC/PPCISelLowering.h
index f5d418cce64..3931384d890 100644
--- a/llvm/lib/Target/PowerPC/PPCISelLowering.h
+++ b/llvm/lib/Target/PowerPC/PPCISelLowering.h
@@ -329,7 +329,7 @@ namespace llvm {
/// DAG node.
virtual const char *getTargetNodeName(unsigned Opcode) const;
- virtual MVT getShiftAmountTy(EVT LHSTy) const { return MVT::i32; }
+ virtual MVT getScalarShiftAmountTy(EVT LHSTy) const { return MVT::i32; }
/// getSetCCResultType - Return the ISD::SETCC ValueType
virtual EVT getSetCCResultType(EVT VT) const;
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