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| author | Hal Finkel <hfinkel@anl.gov> | 2015-01-13 18:25:05 +0000 |
|---|---|---|
| committer | Hal Finkel <hfinkel@anl.gov> | 2015-01-13 18:25:05 +0000 |
| commit | 63fb9281092a475a5d77b52f041efb4d0aa2a26f (patch) | |
| tree | 8388aeaf34312f2566a7c2b494c05dd5e6342a42 /llvm/lib/Target/PowerPC/PPCISelLowering.h | |
| parent | 4a2d333982e9a9b8db9404d65470c5925a6f19b7 (diff) | |
| download | bcm5719-llvm-63fb9281092a475a5d77b52f041efb4d0aa2a26f.tar.gz bcm5719-llvm-63fb9281092a475a5d77b52f041efb4d0aa2a26f.zip | |
Revert "r225808 - [PowerPC] Add StackMap/PatchPoint support"
Reverting this while I investiage buildbot failures (segfaulting in
GetCostForDef at ScheduleDAGRRList.cpp:314).
llvm-svn: 225811
Diffstat (limited to 'llvm/lib/Target/PowerPC/PPCISelLowering.h')
| -rw-r--r-- | llvm/lib/Target/PowerPC/PPCISelLowering.h | 10 |
1 files changed, 4 insertions, 6 deletions
diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.h b/llvm/lib/Target/PowerPC/PPCISelLowering.h index 1b585d8e509..b171b165877 100644 --- a/llvm/lib/Target/PowerPC/PPCISelLowering.h +++ b/llvm/lib/Target/PowerPC/PPCISelLowering.h @@ -570,8 +570,6 @@ namespace llvm { /// expanded to fmul + fadd. bool isFMAFasterThanFMulAndFAdd(EVT VT) const override; - const MCPhysReg *getScratchRegisters(CallingConv::ID CC) const override; - // Should we expand the build vector with shuffles? bool shouldExpandBuildVectorWithShuffles(EVT VT, @@ -683,7 +681,7 @@ namespace llvm { SDLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const; SDValue FinishCall(CallingConv::ID CallConv, SDLoc dl, bool isTailCall, - bool isVarArg, bool IsPatchPoint, + bool isVarArg, SelectionDAG &DAG, SmallVector<std::pair<unsigned, SDValue>, 8> &RegsToPass, @@ -748,7 +746,7 @@ namespace llvm { SDValue LowerCall_Darwin(SDValue Chain, SDValue Callee, CallingConv::ID CallConv, - bool isVarArg, bool isTailCall, bool IsPatchPoint, + bool isVarArg, bool isTailCall, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, const SmallVectorImpl<ISD::InputArg> &Ins, @@ -757,7 +755,7 @@ namespace llvm { SDValue LowerCall_64SVR4(SDValue Chain, SDValue Callee, CallingConv::ID CallConv, - bool isVarArg, bool isTailCall, bool IsPatchPoint, + bool isVarArg, bool isTailCall, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, const SmallVectorImpl<ISD::InputArg> &Ins, @@ -765,7 +763,7 @@ namespace llvm { SmallVectorImpl<SDValue> &InVals) const; SDValue LowerCall_32SVR4(SDValue Chain, SDValue Callee, CallingConv::ID CallConv, - bool isVarArg, bool isTailCall, bool IsPatchPoint, + bool isVarArg, bool isTailCall, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, const SmallVectorImpl<ISD::InputArg> &Ins, |
