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| author | Dan Gohman <gohman@apple.com> | 2007-07-09 20:59:04 +0000 |
|---|---|---|
| committer | Dan Gohman <gohman@apple.com> | 2007-07-09 20:59:04 +0000 |
| commit | f8f531bf69f039bc24f7f804932fd0ca01f084fb (patch) | |
| tree | 64f6ffe149fb8dec6cb4c89c6ea08b1ce9ba174d /llvm/lib/Target/PowerPC/PPCISelLowering.cpp | |
| parent | 3364abbb36ea666ef72351bec890064ab1ed063f (diff) | |
| download | bcm5719-llvm-f8f531bf69f039bc24f7f804932fd0ca01f084fb.tar.gz bcm5719-llvm-f8f531bf69f039bc24f7f804932fd0ca01f084fb.zip | |
Change getCopyToParts and getCopyFromParts to always use target-endian
register ordering, for both physical and virtual registers. Update the PPC
target lowering for calls to expect registers for the call result to
already be in target order.
llvm-svn: 38471
Diffstat (limited to 'llvm/lib/Target/PowerPC/PPCISelLowering.cpp')
| -rw-r--r-- | llvm/lib/Target/PowerPC/PPCISelLowering.cpp | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp index a1fe4602d4d..e3e1e0c66c8 100644 --- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp +++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp @@ -1774,9 +1774,9 @@ static SDOperand LowerCALL(SDOperand Op, SelectionDAG &DAG, case MVT::Other: break; case MVT::i32: if (Op.Val->getValueType(1) == MVT::i32) { - Chain = DAG.getCopyFromReg(Chain, PPC::R4, MVT::i32, InFlag).getValue(1); + Chain = DAG.getCopyFromReg(Chain, PPC::R3, MVT::i32, InFlag).getValue(1); ResultVals[0] = Chain.getValue(0); - Chain = DAG.getCopyFromReg(Chain, PPC::R3, MVT::i32, + Chain = DAG.getCopyFromReg(Chain, PPC::R4, MVT::i32, Chain.getValue(2)).getValue(1); ResultVals[1] = Chain.getValue(0); NumResults = 2; |
