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authorHal Finkel <hfinkel@anl.gov>2013-08-19 05:01:02 +0000
committerHal Finkel <hfinkel@anl.gov>2013-08-19 05:01:02 +0000
commitdbc78e1f736c92102aa66c28286c176d00e4f60c (patch)
tree4ad090e4ba46d2b394a21bb2319c80848eb8f0be /llvm/lib/Target/PowerPC/PPCISelLowering.cpp
parent964157146d53e8221e139ef8134cd6c019a587e1 (diff)
downloadbcm5719-llvm-dbc78e1f736c92102aa66c28286c176d00e4f60c.tar.gz
bcm5719-llvm-dbc78e1f736c92102aa66c28286c176d00e4f60c.zip
Add the PPC fcpsgn instruction
Modern PPC cores support a floating-point copysign instruction, and we can use this to lower the FCOPYSIGN node (which is created from calls to the libm copysign function). A couple of extra patterns are necessary because the operand types of FCOPYSIGN need not agree. llvm-svn: 188653
Diffstat (limited to 'llvm/lib/Target/PowerPC/PPCISelLowering.cpp')
-rw-r--r--llvm/lib/Target/PowerPC/PPCISelLowering.cpp9
1 files changed, 7 insertions, 2 deletions
diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
index 2b83a22ac67..bc55d383f1e 100644
--- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
+++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -149,8 +149,13 @@ PPCTargetLowering::PPCTargetLowering(PPCTargetMachine &TM)
Subtarget->hasFRSQRTES() && Subtarget->hasFRES()))
setOperationAction(ISD::FSQRT, MVT::f32, Expand);
- setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
- setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
+ if (Subtarget->hasFCPSGN()) {
+ setOperationAction(ISD::FCOPYSIGN, MVT::f64, Legal);
+ setOperationAction(ISD::FCOPYSIGN, MVT::f32, Legal);
+ } else {
+ setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
+ setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
+ }
if (Subtarget->hasFPRND()) {
setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
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