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| author | Tom Stellard <thomas.stellard@amd.com> | 2015-07-16 19:40:07 +0000 |
|---|---|---|
| committer | Tom Stellard <thomas.stellard@amd.com> | 2015-07-16 19:40:07 +0000 |
| commit | c98ee20328cd44278c893861d3b5e414f6bff8e0 (patch) | |
| tree | 19a173cbf1cb02023743d71bfe9dab097602c748 /llvm/lib/Target/PowerPC/PPCISelLowering.cpp | |
| parent | eafc4ee6431bef3e551cbd8ef7decb3781ea29f7 (diff) | |
| download | bcm5719-llvm-c98ee20328cd44278c893861d3b5e414f6bff8e0.tar.gz bcm5719-llvm-c98ee20328cd44278c893861d3b5e414f6bff8e0.zip | |
AMDPGU/SI: Use AssertZext node to mask high bit for scratch offsets
Summary:
We can safely assume that the high bit of scratch offsets will never
be set, because this would require at least 128 GB of GPU memory.
Reviewers: arsenm
Subscribers: llvm-commits
Differential Revision: http://reviews.llvm.org/D11225
llvm-svn: 242433
Diffstat (limited to 'llvm/lib/Target/PowerPC/PPCISelLowering.cpp')
0 files changed, 0 insertions, 0 deletions
