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authorAdhemerval Zanella <azanella@linux.vnet.ibm.com>2012-11-05 17:15:56 +0000
committerAdhemerval Zanella <azanella@linux.vnet.ibm.com>2012-11-05 17:15:56 +0000
commitc4182d18905e0b5704e514fddeb294122325bd3d (patch)
tree12c9fd3a0850b9ab81e8ebacb6ab5b8289c36f87 /llvm/lib/Target/PowerPC/PPCISelLowering.cpp
parent520a30fd05dd821204920fcf1f713b1a9bbe60df (diff)
downloadbcm5719-llvm-c4182d18905e0b5704e514fddeb294122325bd3d.tar.gz
bcm5719-llvm-c4182d18905e0b5704e514fddeb294122325bd3d.zip
[PATCH] PowerPC: Expand load extend vector operations
This patch expands the SEXTLOAD, ZEXTLOAD, and EXTLOAD operations for vector types when altivec is enabled. llvm-svn: 167386
Diffstat (limited to 'llvm/lib/Target/PowerPC/PPCISelLowering.cpp')
-rw-r--r--llvm/lib/Target/PowerPC/PPCISelLowering.cpp10
1 files changed, 10 insertions, 0 deletions
diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
index 8d46e96e4d1..0922011d97c 100644
--- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
+++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -361,6 +361,16 @@ PPCTargetLowering::PPCTargetLowering(PPCTargetMachine &TM)
setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
setOperationAction(ISD::CTTZ, VT, Expand);
setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
+ setOperationAction(ISD::SIGN_EXTEND_INREG, VT, Expand);
+
+ for (unsigned j = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
+ j <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++j) {
+ MVT::SimpleValueType InnerVT = (MVT::SimpleValueType)j;
+ setTruncStoreAction(VT, InnerVT, Expand);
+ }
+ setLoadExtAction(ISD::SEXTLOAD, VT, Expand);
+ setLoadExtAction(ISD::ZEXTLOAD, VT, Expand);
+ setLoadExtAction(ISD::EXTLOAD, VT, Expand);
}
for (unsigned i = (unsigned)MVT::FIRST_FP_VECTOR_VALUETYPE;
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