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authorMatt Arsenault <Matthew.Arsenault@amd.com>2015-06-01 05:31:59 +0000
committerMatt Arsenault <Matthew.Arsenault@amd.com>2015-06-01 05:31:59 +0000
commitbd7d80a4a6b70bf303fd9344d3e70bbe1420062a (patch)
tree1aa6a8e53ce6145eb05260d2c74335ac3c244dd2 /llvm/lib/Target/PowerPC/PPCISelLowering.cpp
parent0dba2b399e1cd331f70002f6b922e45bda2b5c2c (diff)
downloadbcm5719-llvm-bd7d80a4a6b70bf303fd9344d3e70bbe1420062a.tar.gz
bcm5719-llvm-bd7d80a4a6b70bf303fd9344d3e70bbe1420062a.zip
Add address space argument to isLegalAddressingMode
This is important because of different addressing modes depending on the address space for GPU targets. This only adds the argument, and does not update any of the uses to provide the correct address space. llvm-svn: 238723
Diffstat (limited to 'llvm/lib/Target/PowerPC/PPCISelLowering.cpp')
-rw-r--r--llvm/lib/Target/PowerPC/PPCISelLowering.cpp3
1 files changed, 2 insertions, 1 deletions
diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
index bb9315e9520..2600ee5db17 100644
--- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
+++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -10825,7 +10825,8 @@ void PPCTargetLowering::LowerAsmOperandForConstraint(SDValue Op,
// isLegalAddressingMode - Return true if the addressing mode represented
// by AM is legal for this target, for a load/store of the specified type.
bool PPCTargetLowering::isLegalAddressingMode(const AddrMode &AM,
- Type *Ty) const {
+ Type *Ty,
+ unsigned AS) const {
// PPC does not allow r+i addressing modes for vectors!
if (Ty->isVectorTy() && AM.BaseOffs != 0)
return false;
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