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authorHal Finkel <hfinkel@anl.gov>2013-08-14 20:05:04 +0000
committerHal Finkel <hfinkel@anl.gov>2013-08-14 20:05:04 +0000
commitb3ca00d2a34302ecf376d5b90ac8627cdbf398df (patch)
tree0adbdf65cdb41feccf43b33d4743f75aeda2ef04 /llvm/lib/Target/PowerPC/PPCISelLowering.cpp
parent83930ac0b7a8dd79059f86fefe08f42c5ebc7b98 (diff)
downloadbcm5719-llvm-b3ca00d2a34302ecf376d5b90ac8627cdbf398df.tar.gz
bcm5719-llvm-b3ca00d2a34302ecf376d5b90ac8627cdbf398df.zip
Actually fix PPC64 64-bit GPR inline asm constraint matching
This is a follow-up to r187693, correcting that code to request the correct register class. The previous version, with the wrong register class, was not really correcting the constraints, but rather was removing them. Coincidentally, this fixed the failing test case in r187693, but obviously created other problems. llvm-svn: 188407
Diffstat (limited to 'llvm/lib/Target/PowerPC/PPCISelLowering.cpp')
-rw-r--r--llvm/lib/Target/PowerPC/PPCISelLowering.cpp2
1 files changed, 1 insertions, 1 deletions
diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
index 886def1b457..2a28d73ee55 100644
--- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
+++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -7591,7 +7591,7 @@ PPCTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
PPC::GPRCRegClass.contains(R.first)) {
const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo();
return std::make_pair(TRI->getMatchingSuperReg(R.first,
- PPC::sub_32, &PPC::GPRCRegClass),
+ PPC::sub_32, &PPC::G8RCRegClass),
&PPC::G8RCRegClass);
}
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