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| author | Lei Huang <lei@ca.ibm.com> | 2018-07-05 04:10:15 +0000 |
|---|---|---|
| committer | Lei Huang <lei@ca.ibm.com> | 2018-07-05 04:10:15 +0000 |
| commit | a26f3be4546ae8cd3dae4fe945a36dca67d53329 (patch) | |
| tree | bdf74cb51d161e1a4f9968a2cfa9681b97995a5a /llvm/lib/Target/PowerPC/PPCISelLowering.cpp | |
| parent | 2db909cfae13f8cab5b02bce5490760e01da96e9 (diff) | |
| download | bcm5719-llvm-a26f3be4546ae8cd3dae4fe945a36dca67d53329.tar.gz bcm5719-llvm-a26f3be4546ae8cd3dae4fe945a36dca67d53329.zip | |
[Power9] Implement float128 parameter passing and return values
This patch enable parameter passing and return by value for float128 types.
Passing aggregate/union which contain float128 members will be submitted in
subsequent patches.
Differential Revision: https://reviews.llvm.org/D47552
llvm-svn: 336306
Diffstat (limited to 'llvm/lib/Target/PowerPC/PPCISelLowering.cpp')
| -rw-r--r-- | llvm/lib/Target/PowerPC/PPCISelLowering.cpp | 11 |
1 files changed, 8 insertions, 3 deletions
diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp index 0fbfa81d828..c494b98da45 100644 --- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp +++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp @@ -806,7 +806,9 @@ PPCTargetLowering::PPCTargetLowering(const PPCTargetMachine &TM, setOperationAction(ISD::FDIV, MVT::f128, Legal); setOperationAction(ISD::FMUL, MVT::f128, Legal); setOperationAction(ISD::FP_EXTEND, MVT::f128, Legal); - setLoadExtAction(ISD::EXTLOAD, MVT::f128, MVT::f64, Expand); + // No extending loads to f128 on PPC. + for (MVT FPT : MVT::fp_valuetypes()) + setLoadExtAction(ISD::EXTLOAD, MVT::f128, FPT, Expand); setOperationAction(ISD::FMA, MVT::f128, Legal); setOperationAction(ISD::FP_ROUND, MVT::f64, Legal); setOperationAction(ISD::FP_ROUND, MVT::f32, Legal); @@ -3152,7 +3154,7 @@ static unsigned CalculateStackSlotAlignment(EVT ArgVT, EVT OrigVT, if (ArgVT == MVT::v4f32 || ArgVT == MVT::v4i32 || ArgVT == MVT::v8i16 || ArgVT == MVT::v16i8 || ArgVT == MVT::v2f64 || ArgVT == MVT::v2i64 || - ArgVT == MVT::v1i128) + ArgVT == MVT::v1i128 || ArgVT == MVT::f128) Align = 16; // QPX vector types stored in double-precision are padded to a 32 byte // boundary. @@ -3232,7 +3234,7 @@ static bool CalculateStackSlotUsed(EVT ArgVT, EVT OrigVT, if (ArgVT == MVT::v4f32 || ArgVT == MVT::v4i32 || ArgVT == MVT::v8i16 || ArgVT == MVT::v16i8 || ArgVT == MVT::v2f64 || ArgVT == MVT::v2i64 || - ArgVT == MVT::v1i128) + ArgVT == MVT::v1i128 || ArgVT == MVT::f128) if (AvailableVRs > 0) { --AvailableVRs; return false; @@ -3821,6 +3823,7 @@ SDValue PPCTargetLowering::LowerFormalArguments_64SVR4( case MVT::v2f64: case MVT::v2i64: case MVT::v1i128: + case MVT::f128: if (!Subtarget.hasQPX()) { // These can be scalar arguments or elements of a vector array type // passed directly. The latter are used to implement ELFv2 homogenous @@ -5536,6 +5539,7 @@ SDValue PPCTargetLowering::LowerCall_64SVR4( case MVT::v2f64: case MVT::v2i64: case MVT::v1i128: + case MVT::f128: if (++NumVRsUsed <= NumVRs) continue; break; @@ -5916,6 +5920,7 @@ SDValue PPCTargetLowering::LowerCall_64SVR4( case MVT::v2f64: case MVT::v2i64: case MVT::v1i128: + case MVT::f128: if (!Subtarget.hasQPX()) { // These can be scalar arguments or elements of a vector array type // passed directly. The latter are used to implement ELFv2 homogenous |
