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authorEvan Cheng <evan.cheng@apple.com>2008-03-08 00:58:38 +0000
committerEvan Cheng <evan.cheng@apple.com>2008-03-08 00:58:38 +0000
commit95cf661534ff6c24e5dba4d156842a00b6af8499 (patch)
treede7a94e33d8a94211cf1e8f56c3b5b32ec731ceb /llvm/lib/Target/PowerPC/PPCISelLowering.cpp
parentd2ab5fd713eb933c48876c1cb9f627a99c64f2b9 (diff)
downloadbcm5719-llvm-95cf661534ff6c24e5dba4d156842a00b6af8499.tar.gz
bcm5719-llvm-95cf661534ff6c24e5dba4d156842a00b6af8499.zip
Implement x86 support for @llvm.prefetch. It corresponds to prefetcht{0|1|2} and prefetchnta instructions.
llvm-svn: 48042
Diffstat (limited to 'llvm/lib/Target/PowerPC/PPCISelLowering.cpp')
-rw-r--r--llvm/lib/Target/PowerPC/PPCISelLowering.cpp1
1 files changed, 1 insertions, 0 deletions
diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
index 06098de0635..15e3f2d0f2a 100644
--- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
+++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -82,6 +82,7 @@ PPCTargetLowering::PPCTargetLowering(PPCTargetMachine &TM)
setOperationAction(ISD::MEMSET, MVT::Other, Expand);
setOperationAction(ISD::MEMCPY, MVT::Other, Expand);
setOperationAction(ISD::MEMBARRIER, MVT::Other, Expand);
+ setOperationAction(ISD::PREFETCH, MVT::Other, Expand);
// PowerPC has no SREM/UREM instructions
setOperationAction(ISD::SREM, MVT::i32, Expand);
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