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| author | Chris Lattner <sabre@nondot.org> | 2006-04-11 01:21:43 +0000 |
|---|---|---|
| committer | Chris Lattner <sabre@nondot.org> | 2006-04-11 01:21:43 +0000 |
| commit | 92533cfb4a8536cd8d069eb9c6943275316a3c8c (patch) | |
| tree | cb4e8ceee8919ff674d4f5a730a4033b9643eff5 /llvm/lib/Target/PowerPC/PPCISelLowering.cpp | |
| parent | c10e9a0250088e7217c0a19095d9056fd1e17e52 (diff) | |
| download | bcm5719-llvm-92533cfb4a8536cd8d069eb9c6943275316a3c8c.tar.gz bcm5719-llvm-92533cfb4a8536cd8d069eb9c6943275316a3c8c.zip | |
Move some return-handling code from lowerarguments to the ISD::RET handling stuff.
No functionality change.
llvm-svn: 27577
Diffstat (limited to 'llvm/lib/Target/PowerPC/PPCISelLowering.cpp')
| -rw-r--r-- | llvm/lib/Target/PowerPC/PPCISelLowering.cpp | 29 |
1 files changed, 9 insertions, 20 deletions
diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp index 135b1792767..f7643b84073 100644 --- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp +++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp @@ -880,12 +880,21 @@ SDOperand PPCTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) { unsigned ArgReg = MVT::isInteger(ArgVT) ? PPC::R3 : PPC::F1; Copy = DAG.getCopyToReg(Op.getOperand(0), ArgReg, Op.getOperand(1), SDOperand()); + + // If we haven't noted the R3/F1 are live out, do so now. + if (DAG.getMachineFunction().liveout_empty()) + DAG.getMachineFunction().addLiveOut(ArgReg); break; } case 3: Copy = DAG.getCopyToReg(Op.getOperand(0), PPC::R3, Op.getOperand(2), SDOperand()); Copy = DAG.getCopyToReg(Copy, PPC::R4, Op.getOperand(1),Copy.getValue(1)); + // If we haven't noted the R3+R4 are live out, do so now. + if (DAG.getMachineFunction().liveout_empty()) { + DAG.getMachineFunction().addLiveOut(PPC::R3); + DAG.getMachineFunction().addLiveOut(PPC::R4); + } break; } return DAG.getNode(PPCISD::RET_FLAG, MVT::Other, Copy, Copy.getValue(1)); @@ -1249,26 +1258,6 @@ PPCTargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) { } } - // Finally, inform the code generator which regs we return values in. - switch (getValueType(F.getReturnType())) { - default: assert(0 && "Unknown type!"); - case MVT::isVoid: break; - case MVT::i1: - case MVT::i8: - case MVT::i16: - case MVT::i32: - MF.addLiveOut(PPC::R3); - break; - case MVT::i64: - MF.addLiveOut(PPC::R3); - MF.addLiveOut(PPC::R4); - break; - case MVT::f32: - case MVT::f64: - MF.addLiveOut(PPC::F1); - break; - } - return ArgValues; } |

