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| author | Craig Topper <craig.topper@intel.com> | 2018-03-06 19:44:52 +0000 |
|---|---|---|
| committer | Craig Topper <craig.topper@intel.com> | 2018-03-06 19:44:52 +0000 |
| commit | 80d3bb3b4be2cc0d3ad25530a83c94ae9c5d1ba7 (patch) | |
| tree | f2356db1943a3a27e7d2dc758d5621e28766d3b4 /llvm/lib/Target/PowerPC/PPCISelLowering.cpp | |
| parent | 091f9eb963c63f4b68ed46725c82e63c21ba0606 (diff) | |
| download | bcm5719-llvm-80d3bb3b4be2cc0d3ad25530a83c94ae9c5d1ba7.tar.gz bcm5719-llvm-80d3bb3b4be2cc0d3ad25530a83c94ae9c5d1ba7.zip | |
[TargetLowering] Rename DAGCombinerInfo::isAfterLegalizeVectorOps to DAGCombiner::isAfterLegalizeDAG since that's what it checks. NFC
The code checks Level == AfterLegalizeDAG which is the fourth and last of the possible DAG combine stages that we have.
There is a Level called AfterLegalVectorOps, but that's the third DAG combine and it doesn't always run.
A function called isAfterLegalVectorOps should imply it returns true in either of the DAG combines that runs after the legalize vector ops stage, but that's not what this function does.
llvm-svn: 326832
Diffstat (limited to 'llvm/lib/Target/PowerPC/PPCISelLowering.cpp')
| -rw-r--r-- | llvm/lib/Target/PowerPC/PPCISelLowering.cpp | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp index 096285c48e4..89a2751f8fe 100644 --- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp +++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp @@ -10982,7 +10982,7 @@ SDValue PPCTargetLowering::ConvertSETCCToSubtract(SDNode *N, // Size of integers being compared has a critical role in the following // analysis, so we prefer to do this when all types are legal. - if (!DCI.isAfterLegalizeVectorOps()) + if (!DCI.isAfterLegalizeDAG()) return SDValue(); // If all users of SETCC extend its value to a legal integer type |
