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authorNicolas Geoffray <nicolas.geoffray@lip6.fr>2007-03-01 13:11:38 +0000
committerNicolas Geoffray <nicolas.geoffray@lip6.fr>2007-03-01 13:11:38 +0000
commit75ab9799df8817c455d4c9e028f2b9c7a7ea14cb (patch)
treea662d2f6da4d3715e46e7c33679ab7771ddbb9be /llvm/lib/Target/PowerPC/PPCISelLowering.cpp
parent105fb1e0dddc884139e8520fb629684ec7ec4d48 (diff)
downloadbcm5719-llvm-75ab9799df8817c455d4c9e028f2b9c7a7ea14cb.tar.gz
bcm5719-llvm-75ab9799df8817c455d4c9e028f2b9c7a7ea14cb.zip
Implemented the frameaddress intrinsic for PPC.
llvm-svn: 34787
Diffstat (limited to 'llvm/lib/Target/PowerPC/PPCISelLowering.cpp')
-rw-r--r--llvm/lib/Target/PowerPC/PPCISelLowering.cpp24
1 files changed, 23 insertions, 1 deletions
diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
index c29364c82f6..38f3974d9a4 100644
--- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
+++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -2700,7 +2700,7 @@ SDOperand PPCTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
// Frame & Return address. Currently unimplemented
case ISD::RETURNADDR: break;
- case ISD::FRAMEADDR: break;
+ case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
}
return SDOperand();
}
@@ -3171,3 +3171,25 @@ bool PPCTargetLowering::isLegalAddressImmediate(int64_t V) const {
bool PPCTargetLowering::isLegalAddressImmediate(llvm::GlobalValue* GV) const {
return TargetLowering::isLegalAddressImmediate(GV);
}
+
+SDOperand PPCTargetLowering::LowerFRAMEADDR(SDOperand Op, SelectionDAG &DAG)
+{
+ // Depths > 0 not supported yet!
+ if (cast<ConstantSDNode>(Op.getOperand(0))->getValue() > 0)
+ return SDOperand();
+
+ MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
+ bool isPPC64 = PtrVT == MVT::i64;
+
+ MachineFunction &MF = DAG.getMachineFunction();
+ MachineFrameInfo *MFI = MF.getFrameInfo();
+ bool is31 = (NoFramePointerElim || MFI->hasVarSizedObjects())
+ && MFI->getStackSize();
+
+ if (isPPC64)
+ return DAG.getCopyFromReg(DAG.getEntryNode(), is31 ? PPC::X31 : PPC::X1,
+ MVT::i32);
+ else
+ return DAG.getCopyFromReg(DAG.getEntryNode(), is31 ? PPC::R31 : PPC::R1,
+ MVT::i32);
+}
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