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authorDuncan Sands <baldrick@free.fr>2008-07-02 17:40:58 +0000
committerDuncan Sands <baldrick@free.fr>2008-07-02 17:40:58 +0000
commit739a0548c46314edb09f5006f18c825ae148e780 (patch)
tree37f1063868df315aac0b351ead4854d8e01d5817 /llvm/lib/Target/PowerPC/PPCISelLowering.cpp
parent9edcf24da9789f5c48276a75062b752fedb56708 (diff)
downloadbcm5719-llvm-739a0548c46314edb09f5006f18c825ae148e780.tar.gz
bcm5719-llvm-739a0548c46314edb09f5006f18c825ae148e780.zip
Add a new getMergeValues method that does not need
to be passed the list of value types, and use this where appropriate. Inappropriate places are where the value type list is already known and may be long, in which case the existing method is more efficient. llvm-svn: 53035
Diffstat (limited to 'llvm/lib/Target/PowerPC/PPCISelLowering.cpp')
-rw-r--r--llvm/lib/Target/PowerPC/PPCISelLowering.cpp12
1 files changed, 6 insertions, 6 deletions
diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
index 482ce63972b..4b2267d8122 100644
--- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
+++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -2752,7 +2752,7 @@ SDOperand PPCTargetLowering::LowerAtomicLOAD_ADD(SDOperand Op, SelectionDAG &DAG
};
SDOperand Store = DAG.getNode(PPCISD::STCX, MVT::Other, Ops2, 4);
SDOperand OutOps[] = { Load, Store };
- return DAG.getMergeValues(DAG.getVTList(VT, MVT::Other), OutOps, 2);
+ return DAG.getMergeValues(OutOps, 2);
}
SDOperand PPCTargetLowering::LowerAtomicCMP_SWAP(SDOperand Op, SelectionDAG &DAG) {
@@ -2794,7 +2794,7 @@ SDOperand PPCTargetLowering::LowerAtomicCMP_SWAP(SDOperand Op, SelectionDAG &DAG
};
SDOperand Store = DAG.getNode(PPCISD::STCX, MVT::Other, Ops3, 4);
SDOperand OutOps[] = { Load, Store };
- return DAG.getMergeValues(DAG.getVTList(VT, MVT::Other), OutOps, 2);
+ return DAG.getMergeValues(OutOps, 2);
}
SDOperand PPCTargetLowering::LowerAtomicSWAP(SDOperand Op, SelectionDAG &DAG) {
@@ -2826,7 +2826,7 @@ SDOperand PPCTargetLowering::LowerAtomicSWAP(SDOperand Op, SelectionDAG &DAG) {
};
SDOperand Store = DAG.getNode(PPCISD::STCX, MVT::Other, Ops2, 4);
SDOperand OutOps[] = { Load, Store };
- return DAG.getMergeValues(DAG.getVTList(VT, MVT::Other), OutOps, 2);
+ return DAG.getMergeValues(OutOps, 2);
}
/// LowerSELECT_CC - Lower floating point select_cc's into fsel instruction when
@@ -3130,7 +3130,7 @@ SDOperand PPCTargetLowering::LowerSHL_PARTS(SDOperand Op, SelectionDAG &DAG) {
SDOperand OutHi = DAG.getNode(ISD::OR, VT, Tmp4, Tmp6);
SDOperand OutLo = DAG.getNode(PPCISD::SHL, VT, Lo, Amt);
SDOperand OutOps[] = { OutLo, OutHi };
- return DAG.getMergeValues(DAG.getVTList(VT, VT), OutOps, 2);
+ return DAG.getMergeValues(OutOps, 2);
}
SDOperand PPCTargetLowering::LowerSRL_PARTS(SDOperand Op, SelectionDAG &DAG) {
@@ -3158,7 +3158,7 @@ SDOperand PPCTargetLowering::LowerSRL_PARTS(SDOperand Op, SelectionDAG &DAG) {
SDOperand OutLo = DAG.getNode(ISD::OR, VT, Tmp4, Tmp6);
SDOperand OutHi = DAG.getNode(PPCISD::SRL, VT, Hi, Amt);
SDOperand OutOps[] = { OutLo, OutHi };
- return DAG.getMergeValues(DAG.getVTList(VT, VT), OutOps, 2);
+ return DAG.getMergeValues(OutOps, 2);
}
SDOperand PPCTargetLowering::LowerSRA_PARTS(SDOperand Op, SelectionDAG &DAG) {
@@ -3186,7 +3186,7 @@ SDOperand PPCTargetLowering::LowerSRA_PARTS(SDOperand Op, SelectionDAG &DAG) {
SDOperand OutLo = DAG.getSelectCC(Tmp5, DAG.getConstant(0, AmtVT),
Tmp4, Tmp6, ISD::SETLE);
SDOperand OutOps[] = { OutLo, OutHi };
- return DAG.getMergeValues(DAG.getVTList(VT, VT), OutOps, 2);
+ return DAG.getMergeValues(OutOps, 2);
}
//===----------------------------------------------------------------------===//
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