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author | Chris Lattner <sabre@nondot.org> | 2006-08-11 16:47:32 +0000 |
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committer | Chris Lattner <sabre@nondot.org> | 2006-08-11 16:47:32 +0000 |
commit | 66f1fbaaada41decf8c60d6ba0de4d38271923df (patch) | |
tree | 6ef1bd18151011dbdc0010c91c6d3b02cbd99eb6 /llvm/lib/Target/PowerPC/PPCISelLowering.cpp | |
parent | 25d0d5c9e0f9714d9791e36596879415d9a16910 (diff) | |
download | bcm5719-llvm-66f1fbaaada41decf8c60d6ba0de4d38271923df.tar.gz bcm5719-llvm-66f1fbaaada41decf8c60d6ba0de4d38271923df.zip |
Fix miscompilation of float vector returns. Compile code to this:
_func:
vsldoi v2, v3, v2, 12
vsldoi v2, v2, v2, 4
blr
instead of:
_func:
vsldoi v2, v3, v2, 12
vsldoi v2, v2, v2, 4
*** vor f1, v2, v2
blr
llvm-svn: 29607
Diffstat (limited to 'llvm/lib/Target/PowerPC/PPCISelLowering.cpp')
-rw-r--r-- | llvm/lib/Target/PowerPC/PPCISelLowering.cpp | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp index 1cb69d1e006..73610fc4826 100644 --- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp +++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp @@ -1238,11 +1238,11 @@ static SDOperand LowerRET(SDOperand Op, SelectionDAG &DAG) { ArgReg = PPC::R3; } else if (ArgVT == MVT::i64) { ArgReg = PPC::X3; - } else if (MVT::isFloatingPoint(ArgVT)) { - ArgReg = PPC::F1; - } else { - assert(MVT::isVector(ArgVT)); + } else if (MVT::isVector(ArgVT)) { ArgReg = PPC::V2; + } else { + assert(MVT::isFloatingPoint(ArgVT)); + ArgReg = PPC::F1; } Copy = DAG.getCopyToReg(Op.getOperand(0), ArgReg, Op.getOperand(1), |