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| author | Adhemerval Zanella <adhemerval.zanella@linaro.org> | 2019-03-18 18:40:07 +0000 |
|---|---|---|
| committer | Adhemerval Zanella <adhemerval.zanella@linaro.org> | 2019-03-18 18:40:07 +0000 |
| commit | 664c1ef52849623ef509e34968e0807a21b7bf15 (patch) | |
| tree | d66a806e4012afe2dce825f3289595becfb0ff9c /llvm/lib/Target/PowerPC/PPCISelLowering.cpp | |
| parent | f6a53d63a10078a5150fd1f9c867e7714ea21417 (diff) | |
| download | bcm5719-llvm-664c1ef52849623ef509e34968e0807a21b7bf15.tar.gz bcm5719-llvm-664c1ef52849623ef509e34968e0807a21b7bf15.zip | |
[TargetLowering] Add code size information on isFPImmLegal. NFC
This allows better code size for aarch64 floating point materialization
in a future patch.
Reviewers: evandro
Differential Revision: https://reviews.llvm.org/D58690
llvm-svn: 356389
Diffstat (limited to 'llvm/lib/Target/PowerPC/PPCISelLowering.cpp')
| -rw-r--r-- | llvm/lib/Target/PowerPC/PPCISelLowering.cpp | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp index c271ed95dd6..d10f8bfb093 100644 --- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp +++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp @@ -14322,7 +14322,8 @@ void PPCTargetLowering::insertSSPDeclarations(Module &M) const { return TargetLowering::insertSSPDeclarations(M); } -bool PPCTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const { +bool PPCTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT, + bool ForCodeSize) const { if (!VT.isSimple() || !Subtarget.hasVSX()) return false; |
