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authorCraig Topper <craig.topper@intel.com>2018-07-30 23:22:00 +0000
committerCraig Topper <craig.topper@intel.com>2018-07-30 23:22:00 +0000
commit2f60ef2c787dfd247956fd826ab5fdfb20b1d1bb (patch)
tree0172aa18f13938bbbb7509ddc242f51dd68715fc /llvm/lib/Target/PowerPC/PPCISelLowering.cpp
parenta2227a3f9a31b9a20e4aa89eefb4344e15156f21 (diff)
downloadbcm5719-llvm-2f60ef2c787dfd247956fd826ab5fdfb20b1d1bb.tar.gz
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[DAGCombiner][TargetLowering] Pass a SmallVector instead of a std::vector to BuildSDIV/BuildUDIV/etc.
The vector contains the SDNodes that these functions create. The number of nodes is always a small number so we should use SmallVector to avoid a heap allocation. llvm-svn: 338329
Diffstat (limited to 'llvm/lib/Target/PowerPC/PPCISelLowering.cpp')
-rw-r--r--llvm/lib/Target/PowerPC/PPCISelLowering.cpp4
1 files changed, 2 insertions, 2 deletions
diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
index b58152a9c18..51ff8a5cf77 100644
--- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
+++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -13104,8 +13104,8 @@ SDValue PPCTargetLowering::PerformDAGCombine(SDNode *N,
SDValue
PPCTargetLowering::BuildSDIVPow2(SDNode *N, const APInt &Divisor,
- SelectionDAG &DAG,
- std::vector<SDNode *> &Created) const {
+ SelectionDAG &DAG,
+ SmallVectorImpl<SDNode *> &Created) const {
// fold (sdiv X, pow2)
EVT VT = N->getValueType(0);
if (VT == MVT::i64 && !Subtarget.isPPC64())
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