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| author | Hal Finkel <hfinkel@anl.gov> | 2013-09-15 15:20:54 +0000 |
|---|---|---|
| committer | Hal Finkel <hfinkel@anl.gov> | 2013-09-15 15:20:54 +0000 |
| commit | 2945d4e91658caf48aa67ebbfe7bf47b8697f6ae (patch) | |
| tree | 30d0b93308883e33e4b8d394fe0ddeeb981fb499 /llvm/lib/Target/PowerPC/PPCISelLowering.cpp | |
| parent | 31658834e67e837ee8940ca1798c42b9296e747a (diff) | |
| download | bcm5719-llvm-2945d4e91658caf48aa67ebbfe7bf47b8697f6ae.tar.gz bcm5719-llvm-2945d4e91658caf48aa67ebbfe7bf47b8697f6ae.zip | |
PPC: Don't restrict lvsl generation to after type legalization
The PPC backend uses a target-specific DAG combine to turn unaligned Altivec
loads into a permutation-based sequence when possible. Unfortunately, the
target-specific DAG combine is not always called on all loads of interest
(sometimes the routines in DAGCombine call CombineTo such that the new node and
users are not added to the worklist); allowing the combine to trigger early
(before type legalization) mitigates this problem. Because the autovectorizers
only create legal vector types, I don't expect a lot of cases where this
optimization is enabled by type legalization in practice.
llvm-svn: 190764
Diffstat (limited to 'llvm/lib/Target/PowerPC/PPCISelLowering.cpp')
| -rw-r--r-- | llvm/lib/Target/PowerPC/PPCISelLowering.cpp | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp index ae046f0b7af..ddad9f82a27 100644 --- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp +++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp @@ -7177,7 +7177,6 @@ SDValue PPCTargetLowering::PerformDAGCombine(SDNode *N, unsigned ABIAlignment = getDataLayout()->getABITypeAlignment(Ty); if (ISD::isNON_EXTLoad(N) && VT.isVector() && TM.getSubtarget<PPCSubtarget>().hasAltivec() && - DCI.getDAGCombineLevel() == AfterLegalizeTypes && LD->getAlignment() < ABIAlignment) { // This is a type-legal unaligned Altivec load. SDValue Chain = LD->getChain(); |
