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| author | Hal Finkel <hfinkel@anl.gov> | 2012-12-25 17:22:53 +0000 |
|---|---|---|
| committer | Hal Finkel <hfinkel@anl.gov> | 2012-12-25 17:22:53 +0000 |
| commit | 1b5ff08d43f0c9d2fe43623990c3cd9e764fb5b0 (patch) | |
| tree | 5668a171af0b44689e94fd468cfbb6c28c4579a3 /llvm/lib/Target/PowerPC/PPCISelLowering.cpp | |
| parent | 84f46d99939eae16035f048339000e12f715421a (diff) | |
| download | bcm5719-llvm-1b5ff08d43f0c9d2fe43623990c3cd9e764fb5b0.tar.gz bcm5719-llvm-1b5ff08d43f0c9d2fe43623990c3cd9e764fb5b0.zip | |
Expand PPC64 atomic load and store
Use of store or load with the atomic specifier on 64-bit types would
cause instruction-selection failures. As with the 32-bit case, these
can use the default expansion in terms of cmp-and-swap.
llvm-svn: 171072
Diffstat (limited to 'llvm/lib/Target/PowerPC/PPCISelLowering.cpp')
| -rw-r--r-- | llvm/lib/Target/PowerPC/PPCISelLowering.cpp | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp index 9cc4e9615d9..b14c1812492 100644 --- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp +++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp @@ -443,6 +443,8 @@ PPCTargetLowering::PPCTargetLowering(PPCTargetMachine &TM) setOperationAction(ISD::ATOMIC_LOAD, MVT::i32, Expand); setOperationAction(ISD::ATOMIC_STORE, MVT::i32, Expand); + setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Expand); + setOperationAction(ISD::ATOMIC_STORE, MVT::i64, Expand); setBooleanContents(ZeroOrOneBooleanContent); setBooleanVectorContents(ZeroOrOneBooleanContent); // FIXME: Is this correct? |
