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author | Li Jia He <hljhehlj@cn.ibm.com> | 2018-11-01 02:35:17 +0000 |
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committer | Li Jia He <hljhehlj@cn.ibm.com> | 2018-11-01 02:35:17 +0000 |
commit | 03170a904f5b5f7f6eb11db4b427c35180e29e2e (patch) | |
tree | 20898bda904c2ce5b22cd5651215795a72b07f75 /llvm/lib/Target/PowerPC/PPCISelLowering.cpp | |
parent | bbaedf2ba1623e730386be258776e47028a21c6e (diff) | |
download | bcm5719-llvm-03170a904f5b5f7f6eb11db4b427c35180e29e2e.tar.gz bcm5719-llvm-03170a904f5b5f7f6eb11db4b427c35180e29e2e.zip |
[PowerPC] Support constraint 'wi' in asm
From the gcc manual, we can see that the specific limit of wi inline asm is “FP or VSX register to hold 64-bit integers for VSX insns or NO_REGS”. The link is https://gcc.gnu.org/onlinedocs/gcc-8.2.0/gcc/Machine-Constraints.html#Machine-Constraints. We should accept this constraint.
Reviewed By: jsji
Differential Revision: https://reviews.llvm.org/D53265
llvm-svn: 345810
Diffstat (limited to 'llvm/lib/Target/PowerPC/PPCISelLowering.cpp')
-rw-r--r-- | llvm/lib/Target/PowerPC/PPCISelLowering.cpp | 8 |
1 files changed, 6 insertions, 2 deletions
diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp index a135667beaa..4ed110e6663 100644 --- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp +++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp @@ -13362,7 +13362,8 @@ PPCTargetLowering::getConstraintType(StringRef Constraint) const { } else if (Constraint == "wc") { // individual CR bits. return C_RegisterClass; } else if (Constraint == "wa" || Constraint == "wd" || - Constraint == "wf" || Constraint == "ws") { + Constraint == "wf" || Constraint == "ws" || + Constraint == "wi") { return C_RegisterClass; // VSX registers. } return TargetLowering::getConstraintType(Constraint); @@ -13392,6 +13393,8 @@ PPCTargetLowering::getSingleConstraintMatchWeight( return CW_Register; else if (StringRef(constraint) == "ws" && type->isDoubleTy()) return CW_Register; + else if (StringRef(constraint) == "wi" && type->isIntegerTy(64)) + return CW_Register; // just hold 64-bit integers data. switch (*constraint) { default: @@ -13474,7 +13477,8 @@ PPCTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, // An individual CR bit. return std::make_pair(0U, &PPC::CRBITRCRegClass); } else if ((Constraint == "wa" || Constraint == "wd" || - Constraint == "wf") && Subtarget.hasVSX()) { + Constraint == "wf" || Constraint == "wi") && + Subtarget.hasVSX()) { return std::make_pair(0U, &PPC::VSRCRegClass); } else if (Constraint == "ws" && Subtarget.hasVSX()) { if (VT == MVT::f32 && Subtarget.hasP8Vector()) |