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authorChris Lattner <sabre@nondot.org>2005-04-02 05:03:24 +0000
committerChris Lattner <sabre@nondot.org>2005-04-02 05:03:24 +0000
commit0b7e4cd107e81db6bac9dc6747df28e8a44a6e66 (patch)
treefaaf4c15cdbd14e5b0dc1b6bc5d8326ce3d2dbba /llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp
parent13fe99c807fd4bf0d0571b47ab08ec03e872044b (diff)
downloadbcm5719-llvm-0b7e4cd107e81db6bac9dc6747df28e8a44a6e66.tar.gz
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This target doesn't support fabs/fneg yet.
llvm-svn: 21010
Diffstat (limited to 'llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp')
-rw-r--r--llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp4
1 files changed, 4 insertions, 0 deletions
diff --git a/llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp b/llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp
index a6ebbadf569..751b5533572 100644
--- a/llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp
+++ b/llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp
@@ -53,6 +53,10 @@ namespace {
// PowerPC has an i16 but no i8 (or i1) SEXTLOAD
setOperationAction(ISD::SEXTLOAD, MVT::i1, Expand);
setOperationAction(ISD::SEXTLOAD, MVT::i8, Expand);
+
+ // We don't support these yet.
+ setOperationAction(ISD::FNEG , MVT::f64 , Expand);
+ setOperationAction(ISD::FABS , MVT::f64 , Expand);
addLegalFPImmediate(+0.0); // Necessary for FSEL
addLegalFPImmediate(-0.0); //
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