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| author | Chris Lattner <sabre@nondot.org> | 2005-04-02 05:03:24 +0000 |
|---|---|---|
| committer | Chris Lattner <sabre@nondot.org> | 2005-04-02 05:03:24 +0000 |
| commit | 0b7e4cd107e81db6bac9dc6747df28e8a44a6e66 (patch) | |
| tree | faaf4c15cdbd14e5b0dc1b6bc5d8326ce3d2dbba /llvm/lib | |
| parent | 13fe99c807fd4bf0d0571b47ab08ec03e872044b (diff) | |
| download | bcm5719-llvm-0b7e4cd107e81db6bac9dc6747df28e8a44a6e66.tar.gz bcm5719-llvm-0b7e4cd107e81db6bac9dc6747df28e8a44a6e66.zip | |
This target doesn't support fabs/fneg yet.
llvm-svn: 21010
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/Alpha/AlphaISelPattern.cpp | 4 | ||||
| -rw-r--r-- | llvm/lib/Target/IA64/IA64ISelPattern.cpp | 3 | ||||
| -rw-r--r-- | llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp | 4 | ||||
| -rw-r--r-- | llvm/lib/Target/X86/X86ISelPattern.cpp | 4 |
4 files changed, 15 insertions, 0 deletions
diff --git a/llvm/lib/Target/Alpha/AlphaISelPattern.cpp b/llvm/lib/Target/Alpha/AlphaISelPattern.cpp index ba5178b6212..7242f8f1fdb 100644 --- a/llvm/lib/Target/Alpha/AlphaISelPattern.cpp +++ b/llvm/lib/Target/Alpha/AlphaISelPattern.cpp @@ -75,6 +75,10 @@ namespace { setOperationAction(ISD::MEMSET , MVT::Other, Expand); setOperationAction(ISD::MEMCPY , MVT::Other, Expand); + // We don't support these yet. + setOperationAction(ISD::FNEG , MVT::f64 , Expand); + setOperationAction(ISD::FABS , MVT::f64 , Expand); + //Doesn't work yet setOperationAction(ISD::SETCC , MVT::f32, Promote); diff --git a/llvm/lib/Target/IA64/IA64ISelPattern.cpp b/llvm/lib/Target/IA64/IA64ISelPattern.cpp index 16607cbcc32..bb31fc7f5c8 100644 --- a/llvm/lib/Target/IA64/IA64ISelPattern.cpp +++ b/llvm/lib/Target/IA64/IA64ISelPattern.cpp @@ -80,6 +80,9 @@ namespace { setOperationAction(ISD::MEMSET , MVT::Other, Expand); setOperationAction(ISD::MEMCPY , MVT::Other, Expand); + // We don't support these yet. + setOperationAction(ISD::FNEG , MVT::f64 , Expand); + setOperationAction(ISD::FABS , MVT::f64 , Expand); computeRegisterProperties(); diff --git a/llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp b/llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp index a6ebbadf569..751b5533572 100644 --- a/llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp +++ b/llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp @@ -53,6 +53,10 @@ namespace { // PowerPC has an i16 but no i8 (or i1) SEXTLOAD setOperationAction(ISD::SEXTLOAD, MVT::i1, Expand); setOperationAction(ISD::SEXTLOAD, MVT::i8, Expand); + + // We don't support these yet. + setOperationAction(ISD::FNEG , MVT::f64 , Expand); + setOperationAction(ISD::FABS , MVT::f64 , Expand); addLegalFPImmediate(+0.0); // Necessary for FSEL addLegalFPImmediate(-0.0); // diff --git a/llvm/lib/Target/X86/X86ISelPattern.cpp b/llvm/lib/Target/X86/X86ISelPattern.cpp index ff23e66c04f..c81b7794f7c 100644 --- a/llvm/lib/Target/X86/X86ISelPattern.cpp +++ b/llvm/lib/Target/X86/X86ISelPattern.cpp @@ -63,6 +63,10 @@ namespace { setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand); setOperationAction(ISD::SEXTLOAD , MVT::i1 , Expand); setOperationAction(ISD::SREM , MVT::f64 , Expand); + + // We don't support these yet. + setOperationAction(ISD::FNEG , MVT::f64 , Expand); + setOperationAction(ISD::FABS , MVT::f64 , Expand); // These should be promoted to a larger select which is supported. /**/ setOperationAction(ISD::SELECT , MVT::i1 , Promote); |
