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| author | Chris Lattner <sabre@nondot.org> | 2005-08-24 23:08:16 +0000 |
|---|---|---|
| committer | Chris Lattner <sabre@nondot.org> | 2005-08-24 23:08:16 +0000 |
| commit | a3fbdae51582aac9d02330e64ae469735a230676 (patch) | |
| tree | 35cd1e68e1bc91d823455d16ac2bac10e627865b /llvm/lib/Target/PowerPC/PPC32CodeEmitter.cpp | |
| parent | 45e1ce4e28333cb7c98100ebcbd525c11a45deea (diff) | |
| download | bcm5719-llvm-a3fbdae51582aac9d02330e64ae469735a230676.tar.gz bcm5719-llvm-a3fbdae51582aac9d02330e64ae469735a230676.zip | |
Split IMPLICIT_DEF into IMPLICIT_DEF_GPR and IMPLICIT_DEF_FP, so that the
instructions take a consistent reg class. Implement ISD::UNDEF in the dag->dag
selector to generate this, fixing UnitTests/2003-07-06-IntOverflow.
llvm-svn: 23028
Diffstat (limited to 'llvm/lib/Target/PowerPC/PPC32CodeEmitter.cpp')
| -rw-r--r-- | llvm/lib/Target/PowerPC/PPC32CodeEmitter.cpp | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/llvm/lib/Target/PowerPC/PPC32CodeEmitter.cpp b/llvm/lib/Target/PowerPC/PPC32CodeEmitter.cpp index a52935a4dfd..25cbda5d4b9 100644 --- a/llvm/lib/Target/PowerPC/PPC32CodeEmitter.cpp +++ b/llvm/lib/Target/PowerPC/PPC32CodeEmitter.cpp @@ -124,7 +124,8 @@ void PPC32CodeEmitter::emitBasicBlock(MachineBasicBlock &MBB) { default: emitWord(getBinaryCodeForInstr(*I)); break; - case PPC::IMPLICIT_DEF: + case PPC::IMPLICIT_DEF_GPR: + case PPC::IMPLICIT_DEF_FP: break; // pseudo opcode, no side effects case PPC::MovePCtoLR: assert(0 && "CodeEmitter does not support MovePCtoLR instruction"); |
