Split IMPLICIT_DEF into IMPLICIT_DEF_GPR and IMPLICIT_DEF_FP, so that the

instructions take a consistent reg class.  Implement ISD::UNDEF in the dag->dag
selector to generate this, fixing UnitTests/2003-07-06-IntOverflow.

llvm-svn: 23028

5 files changed, 21 insertions, 7 deletions

diff --git a/llvm/lib/Target/PowerPC/PPC32CodeEmitter.cpp b/llvm/lib/Target/PowerPC/PPC32CodeEmitter.cpp
index a52935a4dfd..25cbda5d4b9 100644
--- a/llvm/lib/Target/PowerPC/PPC32CodeEmitter.cpp
+++ b/llvm/lib/Target/PowerPC/PPC32CodeEmitter.cpp
@@ -124,7 +124,8 @@ void PPC32CodeEmitter::emitBasicBlock(MachineBasicBlock &MBB) {
     default:
       emitWord(getBinaryCodeForInstr(*I));
       break;
-    case PPC::IMPLICIT_DEF:
+    case PPC::IMPLICIT_DEF_GPR:
+    case PPC::IMPLICIT_DEF_FP:
       break; // pseudo opcode, no side effects
     case PPC::MovePCtoLR:
       assert(0 && "CodeEmitter does not support MovePCtoLR instruction");
diff --git a/llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp b/llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp
index 4e753d1d1b4..22082a45f0b 100644
--- a/llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp
+++ b/llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp
@@ -830,7 +830,10 @@ unsigned ISel::SelectExpr(SDOperand N, bool Recording) {
     Node->dump(); std::cerr << '\n';
     assert(0 && "Node not handled!\n");
   case ISD::UNDEF:
-    BuildMI(BB, PPC::IMPLICIT_DEF, 0, Result);
+    if (Node->getValueType(0) == MVT::i32)
+      BuildMI(BB, PPC::IMPLICIT_DEF_GPR, 0, Result);
+    else
+      BuildMI(BB, PPC::IMPLICIT_DEF_FP, 0, Result);
     return Result;
   case ISD::DYNAMIC_STACKALLOC:
     // Generate both result values.  FIXME: Need a better commment here?
@@ -1872,8 +1875,11 @@ void ISel::Select(SDOperand N) {
     return;
   case ISD::ImplicitDef:
     Select(N.getOperand(0));
-    BuildMI(BB, PPC::IMPLICIT_DEF, 0,
-            cast<RegisterSDNode>(N.getOperand(1))->getReg());
+    Tmp1 = cast<RegisterSDNode>(N.getOperand(1))->getReg();
+    if (N.getOperand(1).getValueType() == MVT::i32)
+      BuildMI(BB, PPC::IMPLICIT_DEF_GPR, 0, Tmp1);
+    else
+      BuildMI(BB, PPC::IMPLICIT_DEF_FP, 0, Tmp1);
     return;
   case ISD::RET:
     switch (N.getNumOperands()) {
diff --git a/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp b/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
index b6ce27ae83d..161d17d0d6f 100644
--- a/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
+++ b/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
@@ -469,7 +469,6 @@ SDOperand PPC32DAGToDAGISel::Select(SDOperand Op) {
     std::cerr << "\n";
     abort();
   case ISD::EntryToken:       // These leaves remain the same.
-  case ISD::UNDEF:
     return Op;
   case ISD::TokenFactor: {
     SDOperand New;
@@ -525,6 +524,12 @@ SDOperand PPC32DAGToDAGISel::Select(SDOperand Op) {
     }
     break;
   }
+  case ISD::UNDEF:
+    if (N->getValueType(0) == MVT::i32)
+      CurDAG->SelectNodeTo(N, MVT::i32, PPC::IMPLICIT_DEF_GPR);
+    else
+      CurDAG->SelectNodeTo(N, N->getValueType(0), PPC::IMPLICIT_DEF_FP);
+    break;
   case ISD::GlobalAddress: {
     GlobalValue *GV = cast<GlobalAddressSDNode>(N)->getGlobal();
     SDOperand Tmp;
diff --git a/llvm/lib/Target/PowerPC/PowerPCBranchSelector.cpp b/llvm/lib/Target/PowerPC/PowerPCBranchSelector.cpp
index b80ab5e9d7c..9a29eec55f4 100644
--- a/llvm/lib/Target/PowerPC/PowerPCBranchSelector.cpp
+++ b/llvm/lib/Target/PowerPC/PowerPCBranchSelector.cpp
@@ -40,7 +40,8 @@ namespace {
         // minor pessimization that saves us from having to worry about
         // keeping the offsets up to date later when we emit long branch glue.
         return 12;
-      case PPC::IMPLICIT_DEF: // no asm emitted
+      case PPC::IMPLICIT_DEF_GPR: // no asm emitted
+      case PPC::IMPLICIT_DEF_FP: // no asm emitted
         return 0;
       default:
         break;
diff --git a/llvm/lib/Target/PowerPC/PowerPCInstrInfo.td b/llvm/lib/Target/PowerPC/PowerPCInstrInfo.td
index a42ccf30503..b0a8b3b9ee7 100644
--- a/llvm/lib/Target/PowerPC/PowerPCInstrInfo.td
+++ b/llvm/lib/Target/PowerPC/PowerPCInstrInfo.td
@@ -64,7 +64,8 @@ let isLoad = 1 in {
 def ADJCALLSTACKDOWN : Pseudo<(ops u16imm), "; ADJCALLSTACKDOWN">;
 def ADJCALLSTACKUP : Pseudo<(ops u16imm), "; ADJCALLSTACKUP">;
 }
-def IMPLICIT_DEF : Pseudo<(ops variable_ops), "; IMPLICIT_DEF">;
+def IMPLICIT_DEF_GPR : Pseudo<(ops GPRC:$rD), "; $rD = IMPLICIT_DEF_GPRC">;
+def IMPLICIT_DEF_FP  : Pseudo<(ops FPRC:$rD), "; %rD = IMPLICIT_DEF_FP">;
 
 let Defs = [LR] in
   def MovePCtoLR : Pseudo<(ops piclabel:$label), "bl $label">;