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authorUlrich Weigand <ulrich.weigand@de.ibm.com>2013-03-26 10:53:27 +0000
committerUlrich Weigand <ulrich.weigand@de.ibm.com>2013-03-26 10:53:27 +0000
commit63aa852a84fa61247c84a74d083f036fd06e352b (patch)
treed94a4412451d8952f1071e5d0f0cbd5d8166d9c1 /llvm/lib/Target/PowerPC/MCTargetDesc/PPCPredicates.h
parent410a40bb5fcb20db4735d68f922819da7c72f16d (diff)
downloadbcm5719-llvm-63aa852a84fa61247c84a74d083f036fd06e352b.tar.gz
bcm5719-llvm-63aa852a84fa61247c84a74d083f036fd06e352b.zip
PowerPC: Simplify BLR pattern.
The BLR pattern cannot be recognized by the asm parser in its current form. This complexity is due to an apparent attempt to enable conditional BLR variants. However, none of those can ever be generated by current code; the pattern is only ever created using the default "pred" operand. To simplify the pattern and allow it to be recognized by the parser, this commit removes those attempts at conditional BLR support. When we later come back to actually add real conditional BLR, this should probably be done via a fully generic conditional branch pattern. No change in generated code. llvm-svn: 178002
Diffstat (limited to 'llvm/lib/Target/PowerPC/MCTargetDesc/PPCPredicates.h')
-rw-r--r--llvm/lib/Target/PowerPC/MCTargetDesc/PPCPredicates.h1
1 files changed, 0 insertions, 1 deletions
diff --git a/llvm/lib/Target/PowerPC/MCTargetDesc/PPCPredicates.h b/llvm/lib/Target/PowerPC/MCTargetDesc/PPCPredicates.h
index b0680fbb8c6..ad2b0181281 100644
--- a/llvm/lib/Target/PowerPC/MCTargetDesc/PPCPredicates.h
+++ b/llvm/lib/Target/PowerPC/MCTargetDesc/PPCPredicates.h
@@ -25,7 +25,6 @@ namespace llvm {
namespace PPC {
/// Predicate - These are "(BI << 5) | BO" for various predicates.
enum Predicate {
- PRED_ALWAYS = (0 << 5) | 20,
PRED_LT = (0 << 5) | 12,
PRED_LE = (1 << 5) | 4,
PRED_EQ = (2 << 5) | 12,
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