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| author | Simon Dardis <simon.dardis@mips.com> | 2018-02-20 15:55:17 +0000 |
|---|---|---|
| committer | Simon Dardis <simon.dardis@mips.com> | 2018-02-20 15:55:17 +0000 |
| commit | d3860e66701cf4046c1f3562b631a8bc474f4af4 (patch) | |
| tree | 2281ef52ad547c67da2c12dd68fa94584acbd46b /llvm/lib/Target/Mips | |
| parent | 59a9856e06c1f8eb648daa877d3e05d23564dfc5 (diff) | |
| download | bcm5719-llvm-d3860e66701cf4046c1f3562b631a8bc474f4af4.tar.gz bcm5719-llvm-d3860e66701cf4046c1f3562b631a8bc474f4af4.zip | |
[mips] Correct the definition of cvt.d.w
An upcoming patch D41434, changes the ordering of the matcher table
for assembly. This patch corrects the definition of the normal MIPS
cvt.d.w not to be available in microMIPS.
llvm-svn: 325589
Diffstat (limited to 'llvm/lib/Target/Mips')
| -rw-r--r-- | llvm/lib/Target/Mips/MipsInstrFPU.td | 5 |
1 files changed, 2 insertions, 3 deletions
diff --git a/llvm/lib/Target/Mips/MipsInstrFPU.td b/llvm/lib/Target/Mips/MipsInstrFPU.td index 23fa4566106..af7e4a1d263 100644 --- a/llvm/lib/Target/Mips/MipsInstrFPU.td +++ b/llvm/lib/Target/Mips/MipsInstrFPU.td @@ -425,10 +425,9 @@ let AdditionalPredicates = [NotInMicroMips] in { ABSS_FM<0x20, 17>, FGR_32; def CVT_D32_S : MMRel, ABSS_FT<"cvt.d.s", AFGR64Opnd, FGR32Opnd, II_CVT>, ABSS_FM<0x21, 16>, FGR_32; + def CVT_D32_W : MMRel, ABSS_FT<"cvt.d.w", AFGR64Opnd, FGR32Opnd, II_CVT>, + ABSS_FM<0x21, 20>, FGR_32; } -def CVT_D32_W : MMRel, ABSS_FT<"cvt.d.w", AFGR64Opnd, FGR32Opnd, II_CVT>, - ABSS_FM<0x21, 20>, FGR_32; - let DecoderNamespace = "MipsFP64" in { let AdditionalPredicates = [NotInMicroMips] in { def CVT_S_L : ABSS_FT<"cvt.s.l", FGR32Opnd, FGR64Opnd, II_CVT>, |
