[mips] Correct the definition of cvt.d.w

An upcoming patch D41434, changes the ordering of the matcher table
for assembly. This patch corrects the definition of the normal MIPS
cvt.d.w not to be available in microMIPS.

llvm-svn: 325589

3 files changed, 10 insertions, 7 deletions

diff --git a/llvm/lib/Target/Mips/MipsInstrFPU.td b/llvm/lib/Target/Mips/MipsInstrFPU.td
index 23fa4566106..af7e4a1d263 100644
--- a/llvm/lib/Target/Mips/MipsInstrFPU.td
+++ b/llvm/lib/Target/Mips/MipsInstrFPU.td
@@ -425,10 +425,9 @@ let AdditionalPredicates = [NotInMicroMips] in {
                   ABSS_FM<0x20, 17>, FGR_32;
   def CVT_D32_S : MMRel, ABSS_FT<"cvt.d.s", AFGR64Opnd, FGR32Opnd, II_CVT>,
                   ABSS_FM<0x21, 16>, FGR_32;
+  def CVT_D32_W : MMRel, ABSS_FT<"cvt.d.w", AFGR64Opnd, FGR32Opnd, II_CVT>,
+                  ABSS_FM<0x21, 20>, FGR_32;
 }
-def CVT_D32_W : MMRel, ABSS_FT<"cvt.d.w", AFGR64Opnd, FGR32Opnd, II_CVT>,
-                ABSS_FM<0x21, 20>, FGR_32;
-
 let DecoderNamespace = "MipsFP64" in {
   let AdditionalPredicates = [NotInMicroMips] in {
     def CVT_S_L   : ABSS_FT<"cvt.s.l", FGR32Opnd, FGR64Opnd, II_CVT>,
diff --git a/llvm/test/MC/Mips/micromips-fpu-instructions.s b/llvm/test/MC/Mips/micromips-fpu-instructions.s
index 0aeb326b431..8843e3b6b34 100644
--- a/llvm/test/MC/Mips/micromips-fpu-instructions.s
+++ b/llvm/test/MC/Mips/micromips-fpu-instructions.s
@@ -1,6 +1,6 @@
-# RUN: llvm-mc %s -triple=mipsel -show-encoding -mattr=micromips \
+# RUN: llvm-mc %s -triple=mipsel -show-encoding -show-inst -mattr=micromips \
 # RUN: -mcpu=mips32r2 | FileCheck -check-prefix=CHECK-EL %s
-# RUN: llvm-mc %s -triple=mips -show-encoding -mattr=micromips \
+# RUN: llvm-mc %s -triple=mips -show-encoding -show-inst -mattr=micromips \
 # RUN: -mcpu=mips32r2 | FileCheck -check-prefix=CHECK-EB %s
 # Check that the assembler can handle the documented syntax
 # for fpu instructions
@@ -47,6 +47,7 @@
 # CHECK-EL: neg.d      $f6, $f8         # encoding: [0xc8,0x54,0x7b,0x2b]
 # CHECK-EL: cvt.d.s    $f6, $f8         # encoding: [0xc8,0x54,0x7b,0x13]
 # CHECK-EL: cvt.d.w    $f6, $f8         # encoding: [0xc8,0x54,0x7b,0x33]
+# CHECK-EL:                             # <MCInst #{{.*}} CVT_D32_W_MM
 # CHECK-EL: cvt.s.d    $f6, $f8         # encoding: [0xc8,0x54,0x7b,0x1b]
 # CHECK-EL: cvt.s.w    $f6, $f8         # encoding: [0xc8,0x54,0x7b,0x3b]
 # CHECK-EL: cfc1    $6, $0              # encoding: [0xc0,0x54,0x3b,0x10]
@@ -112,6 +113,7 @@
 # CHECK-EB: neg.d $f6, $f8              # encoding: [0x54,0xc8,0x2b,0x7b]
 # CHECK-EB: cvt.d.s $f6, $f8            # encoding: [0x54,0xc8,0x13,0x7b]
 # CHECK-EB: cvt.d.w $f6, $f8            # encoding: [0x54,0xc8,0x33,0x7b]
+# CHECK-EB:                             # <MCInst #{{.*}} CVT_D32_W_MM
 # CHECK-EB: cvt.s.d $f6, $f8            # encoding: [0x54,0xc8,0x1b,0x7b]
 # CHECK-EB: cvt.s.w $f6, $f8            # encoding: [0x54,0xc8,0x3b,0x7b]
 # CHECK-EB: cfc1    $6, $0              # encoding: [0x54,0xc0,0x10,0x3b]
diff --git a/llvm/test/MC/Mips/mips-fpu-instructions.s b/llvm/test/MC/Mips/mips-fpu-instructions.s
index 7c497171781..733231afb79 100644
--- a/llvm/test/MC/Mips/mips-fpu-instructions.s
+++ b/llvm/test/MC/Mips/mips-fpu-instructions.s
@@ -1,5 +1,5 @@
-# RUN: llvm-mc  %s -triple=mipsel-unknown-linux -show-encoding -mcpu=mips32r2 | FileCheck %s
-# RUN: llvm-mc  %s -triple=mips64el-unknown-linux -show-encoding -mcpu=mips64r2 | FileCheck %s
+# RUN: llvm-mc  %s -triple=mipsel-unknown-linux -show-encoding -show-inst -mcpu=mips32r2 | FileCheck %s --check-prefixes=CHECK,CHECK-32
+# RUN: llvm-mc  %s -triple=mips64el-unknown-linux -show-encoding -show-inst -mcpu=mips64r2 | FileCheck %s --check-prefixes=CHECK,CHECK-64
 # Check that the assembler can handle the documented syntax
 # for FPU instructions.
 #------------------------------------------------------------------------------
@@ -123,6 +123,8 @@
 #------------------------------------------------------------------------------
 # CHECK:  cvt.d.s   $f6, $f7          # encoding: [0xa1,0x39,0x00,0x46]
 # CHECK:  cvt.d.w   $f12, $f14        # encoding: [0x21,0x73,0x80,0x46]
+# CHECK-32:                           # <MCInst #{{.*}} CVT_D32_W
+# CHECK-64:                           # <MCInst #{{.*}} CVT_D64_W
 # CHECK:  cvt.s.d   $f12, $f14        # encoding: [0x20,0x73,0x20,0x46]
 # CHECK:  cvt.s.w   $f6, $f7          # encoding: [0xa0,0x39,0x80,0x46]
 # CHECK:  cvt.w.d   $f12, $f14        # encoding: [0x24,0x73,0x20,0x46]