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| author | Hrvoje Varga <Hrvoje.Varga@imgtec.com> | 2016-05-12 12:46:06 +0000 |
|---|---|---|
| committer | Hrvoje Varga <Hrvoje.Varga@imgtec.com> | 2016-05-12 12:46:06 +0000 |
| commit | cf6a78192ba35ef43662558abe121a945e9dd617 (patch) | |
| tree | e79254b942cc2eb4588596c5f4b37d3250d9dac3 /llvm/lib/Target/Mips/MipsInstrFPU.td | |
| parent | 2615c9e535225994eb75d1b35effe092a7ac6293 (diff) | |
| download | bcm5719-llvm-cf6a78192ba35ef43662558abe121a945e9dd617.tar.gz bcm5719-llvm-cf6a78192ba35ef43662558abe121a945e9dd617.zip | |
Revert "[mips][microMIPS] Implement CFC*, CTC* and LDC* instructions"
This reverts commit r269176 as it caused test-suite failure.
llvm-svn: 269287
Diffstat (limited to 'llvm/lib/Target/Mips/MipsInstrFPU.td')
| -rw-r--r-- | llvm/lib/Target/Mips/MipsInstrFPU.td | 15 |
1 files changed, 5 insertions, 10 deletions
diff --git a/llvm/lib/Target/Mips/MipsInstrFPU.td b/llvm/lib/Target/Mips/MipsInstrFPU.td index 165d853eb98..8e58272dc6e 100644 --- a/llvm/lib/Target/Mips/MipsInstrFPU.td +++ b/llvm/lib/Target/Mips/MipsInstrFPU.td @@ -404,19 +404,14 @@ def LWC1 : MMRel, LW_FT<"lwc1", FGR32Opnd, II_LWC1, load>, LW_FM<0x31>; def SWC1 : MMRel, SW_FT<"swc1", FGR32Opnd, II_SWC1, store>, LW_FM<0x39>; let DecoderNamespace = "Mips64" in { - let AdditionalPredicates = [NotInMicroMips] in { - def LDC164 : StdMMR6Rel, LW_FT<"ldc1", FGR64Opnd, II_LDC1, load>, - LW_FM<0x35>, ISA_MIPS2, FGR_64 { - let BaseOpcode = "LDC164"; - } - } + def LDC164 : LW_FT<"ldc1", FGR64Opnd, II_LDC1, load>, LW_FM<0x35>, ISA_MIPS2, + FGR_64; def SDC164 : SW_FT<"sdc1", FGR64Opnd, II_SDC1, store>, LW_FM<0x3d>, ISA_MIPS2, FGR_64; } -def LDC1 : MMRel, StdMMR6Rel, LW_FT<"ldc1", AFGR64Opnd, II_LDC1, load>, - LW_FM<0x35>, ISA_MIPS2, FGR_32 { - let BaseOpcode = "LDC132"; -} + +def LDC1 : MMRel, LW_FT<"ldc1", AFGR64Opnd, II_LDC1, load>, LW_FM<0x35>, + ISA_MIPS2, FGR_32; def SDC1 : MMRel, SW_FT<"sdc1", AFGR64Opnd, II_SDC1, store>, LW_FM<0x3d>, ISA_MIPS2, FGR_32; |
