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authorDaniel Sanders <daniel.sanders@imgtec.com>2016-05-06 12:57:26 +0000
committerDaniel Sanders <daniel.sanders@imgtec.com>2016-05-06 12:57:26 +0000
commita6cda12179b881731106ee86ee9600e45f6db5d6 (patch)
tree89b28e6c6d28f036d068cad46387817df094641a /llvm/lib/Target/Mips/MipsFastISel.cpp
parenta139f8612879cd7619843ef305e0d68ba59e1cd0 (diff)
downloadbcm5719-llvm-a6cda12179b881731106ee86ee9600e45f6db5d6.tar.gz
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[mips][fastisel] Conditional moves do not have implicit operands.
Reviewers: sdardis Subscribers: dsanders, sdardis, llvm-commits Differential Revision: http://reviews.llvm.org/D19862 llvm-svn: 268730
Diffstat (limited to 'llvm/lib/Target/Mips/MipsFastISel.cpp')
-rw-r--r--llvm/lib/Target/Mips/MipsFastISel.cpp9
1 files changed, 4 insertions, 5 deletions
diff --git a/llvm/lib/Target/Mips/MipsFastISel.cpp b/llvm/lib/Target/Mips/MipsFastISel.cpp
index d215ed7977d..f8535290d3b 100644
--- a/llvm/lib/Target/Mips/MipsFastISel.cpp
+++ b/llvm/lib/Target/Mips/MipsFastISel.cpp
@@ -692,11 +692,10 @@ bool MipsFastISel::emitCmp(unsigned ResultReg, const CmpInst *CI) {
emitInst(Mips::ADDiu, RegWithOne).addReg(Mips::ZERO).addImm(1);
emitInst(Opc).addReg(LeftReg).addReg(RightReg).addReg(
Mips::FCC0, RegState::ImplicitDefine);
- MachineInstrBuilder MI = emitInst(CondMovOpc, ResultReg)
- .addReg(RegWithOne)
- .addReg(Mips::FCC0)
- .addReg(RegWithZero, RegState::Implicit);
- MI->tieOperands(0, 3);
+ emitInst(CondMovOpc, ResultReg)
+ .addReg(RegWithOne)
+ .addReg(Mips::FCC0)
+ .addReg(RegWithZero);
break;
}
}
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