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| author | Simon Dardis <simon.dardis@mips.com> | 2018-05-25 16:15:48 +0000 |
|---|---|---|
| committer | Simon Dardis <simon.dardis@mips.com> | 2018-05-25 16:15:48 +0000 |
| commit | 6a3199238371e86d8251502c001fe9b0e8ba5795 (patch) | |
| tree | db95a378bf22265a66e6b8566cdaf2a036056a07 /llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp | |
| parent | a185c719599e4911d61e044095eb8f9d7ab38aa3 (diff) | |
| download | bcm5719-llvm-6a3199238371e86d8251502c001fe9b0e8ba5795.tar.gz bcm5719-llvm-6a3199238371e86d8251502c001fe9b0e8ba5795.zip | |
[mips] Fix the definitions of lwp, swp
Rather than using a regpair operand of these instructions, use two seperate
operands and a custom converter to handle the implicit second register operand.
Additionally, remove the microMIPS32R6 definition as its redundant.
Reviewers: atanasyan, abeserminji, smaksimovic
Differential Revision: https://reviews.llvm.org/D47255
llvm-svn: 333288
Diffstat (limited to 'llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp')
| -rw-r--r-- | llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp b/llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp index eb2c33d2f4c..b94afb9520e 100644 --- a/llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp +++ b/llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp @@ -1895,8 +1895,7 @@ static DecodeStatus DecodeMemMMImm12(MCInst &Inst, LLVM_FALLTHROUGH; default: Inst.addOperand(MCOperand::createReg(Reg)); - if (Inst.getOpcode() == Mips::LWP_MM || Inst.getOpcode() == Mips::SWP_MM || - Inst.getOpcode() == Mips::LWP_MMR6 || Inst.getOpcode() == Mips::SWP_MMR6) + if (Inst.getOpcode() == Mips::LWP_MM || Inst.getOpcode() == Mips::SWP_MM) Inst.addOperand(MCOperand::createReg(Reg+1)); Inst.addOperand(MCOperand::createReg(Base)); |
