From 6a3199238371e86d8251502c001fe9b0e8ba5795 Mon Sep 17 00:00:00 2001 From: Simon Dardis Date: Fri, 25 May 2018 16:15:48 +0000 Subject: [mips] Fix the definitions of lwp, swp Rather than using a regpair operand of these instructions, use two seperate operands and a custom converter to handle the implicit second register operand. Additionally, remove the microMIPS32R6 definition as its redundant. Reviewers: atanasyan, abeserminji, smaksimovic Differential Revision: https://reviews.llvm.org/D47255 llvm-svn: 333288 --- llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) (limited to 'llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp') diff --git a/llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp b/llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp index eb2c33d2f4c..b94afb9520e 100644 --- a/llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp +++ b/llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp @@ -1895,8 +1895,7 @@ static DecodeStatus DecodeMemMMImm12(MCInst &Inst, LLVM_FALLTHROUGH; default: Inst.addOperand(MCOperand::createReg(Reg)); - if (Inst.getOpcode() == Mips::LWP_MM || Inst.getOpcode() == Mips::SWP_MM || - Inst.getOpcode() == Mips::LWP_MMR6 || Inst.getOpcode() == Mips::SWP_MMR6) + if (Inst.getOpcode() == Mips::LWP_MM || Inst.getOpcode() == Mips::SWP_MM) Inst.addOperand(MCOperand::createReg(Reg+1)); Inst.addOperand(MCOperand::createReg(Base)); -- cgit v1.2.3