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| author | Krzysztof Parzyszek <kparzysz@codeaurora.org> | 2017-11-29 19:58:10 +0000 |
|---|---|---|
| committer | Krzysztof Parzyszek <kparzysz@codeaurora.org> | 2017-11-29 19:58:10 +0000 |
| commit | 6a8e5f4b0f3759abe3a0ab1da99a15d413ef6dde (patch) | |
| tree | b5aba33b939c6860e81e8ee79046c2b20adebb19 /llvm/lib/Target/Hexagon/HexagonISelLowering.h | |
| parent | cf5b4af8200067c9154aa20cf1fb1d4a57c601ff (diff) | |
| download | bcm5719-llvm-6a8e5f4b0f3759abe3a0ab1da99a15d413ef6dde.tar.gz bcm5719-llvm-6a8e5f4b0f3759abe3a0ab1da99a15d413ef6dde.zip | |
[Hexagon] Create helpers extractVector and insertVector in lowering
llvm-svn: 319351
Diffstat (limited to 'llvm/lib/Target/Hexagon/HexagonISelLowering.h')
| -rw-r--r-- | llvm/lib/Target/Hexagon/HexagonISelLowering.h | 25 |
1 files changed, 21 insertions, 4 deletions
diff --git a/llvm/lib/Target/Hexagon/HexagonISelLowering.h b/llvm/lib/Target/Hexagon/HexagonISelLowering.h index b76fd0c1592..781e49ab2d0 100644 --- a/llvm/lib/Target/Hexagon/HexagonISelLowering.h +++ b/llvm/lib/Target/Hexagon/HexagonISelLowering.h @@ -117,13 +117,17 @@ namespace HexagonISD { SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override; const char *getTargetNodeName(unsigned Opcode) const override; + + SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const; SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const; - SDValue LowerEXTRACT_VECTOR(SDValue Op, SelectionDAG &DAG) const; + SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const; + SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const; SDValue LowerEXTRACT_SUBVECTOR_HVX(SDValue Op, SelectionDAG &DAG) const; - SDValue LowerINSERT_VECTOR(SDValue Op, SelectionDAG &DAG) const; + SDValue LowerINSERT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const; + SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const; SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const; SDValue LowerVECTOR_SHIFT(SDValue Op, SelectionDAG &DAG) const; - SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const; + SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const; SDValue LowerINLINEASM(SDValue Op, SelectionDAG &DAG) const; SDValue LowerPREFETCH(SDValue Op, SelectionDAG &DAG) const; @@ -269,11 +273,24 @@ namespace HexagonISD { return AtomicExpansionKind::LLSC; } - protected: + private: + MVT ty(SDValue Op) const { + return Op.getValueType().getSimpleVT(); + } + MVT tyScalar(MVT Ty) const { + if (!Ty.isVector()) + return Ty; + return MVT::getIntegerVT(Ty.getSizeInBits()); + } + SDValue buildVector32(ArrayRef<SDValue> Elem, const SDLoc &dl, MVT VecTy, SelectionDAG &DAG) const; SDValue buildVector64(ArrayRef<SDValue> Elem, const SDLoc &dl, MVT VecTy, SelectionDAG &DAG) const; + SDValue extractVector(SDValue VecV, SDValue IdxV, const SDLoc &dl, + MVT ValTy, MVT ResTy, SelectionDAG &DAG) const; + SDValue insertVector(SDValue VecV, SDValue ValV, SDValue IdxV, + const SDLoc &dl, MVT ValTy, SelectionDAG &DAG) const; std::pair<const TargetRegisterClass*, uint8_t> findRepresentativeClass(const TargetRegisterInfo *TRI, MVT VT) |
