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authorKrzysztof Parzyszek <kparzysz@codeaurora.org>2016-03-28 15:43:03 +0000
committerKrzysztof Parzyszek <kparzysz@codeaurora.org>2016-03-28 15:43:03 +0000
commit2d65ea74dcd26fe6468944900b7d6f762f64e54c (patch)
tree1119f4797d218784f56b87cea58c13b62d0bc9be /llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
parent01f2ca5612127b4ff44e3eb4a63da24627341df8 (diff)
downloadbcm5719-llvm-2d65ea74dcd26fe6468944900b7d6f762f64e54c.tar.gz
bcm5719-llvm-2d65ea74dcd26fe6468944900b7d6f762f64e54c.zip
[Hexagon] Improve handling of unaligned vector loads and stores
llvm-svn: 264584
Diffstat (limited to 'llvm/lib/Target/Hexagon/HexagonISelLowering.cpp')
-rw-r--r--llvm/lib/Target/Hexagon/HexagonISelLowering.cpp26
1 files changed, 26 insertions, 0 deletions
diff --git a/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp b/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
index 75244391fdd..f6ce321d5e5 100644
--- a/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
@@ -3019,6 +3019,32 @@ bool llvm::isPositiveHalfWord(SDNode *N) {
}
}
+bool HexagonTargetLowering::allowsMisalignedMemoryAccesses(EVT VT,
+ unsigned AS, unsigned Align, bool *Fast) const {
+ if (Fast)
+ *Fast = false;
+
+ switch (VT.getSimpleVT().SimpleTy) {
+ default:
+ return false;
+ case MVT::v64i8:
+ case MVT::v128i8:
+ case MVT::v256i8:
+ case MVT::v32i16:
+ case MVT::v64i16:
+ case MVT::v128i16:
+ case MVT::v16i32:
+ case MVT::v32i32:
+ case MVT::v64i32:
+ case MVT::v8i64:
+ case MVT::v16i64:
+ case MVT::v32i64:
+ return true;
+ }
+ return false;
+}
+
+
std::pair<const TargetRegisterClass*, uint8_t>
HexagonTargetLowering::findRepresentativeClass(const TargetRegisterInfo *TRI,
MVT VT) const {
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