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author | Duncan Sands <baldrick@free.fr> | 2011-09-06 19:07:46 +0000 |
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committer | Duncan Sands <baldrick@free.fr> | 2011-09-06 19:07:46 +0000 |
commit | f2641e1bc11b28db5722f7f6adec2ac416dd0f6c (patch) | |
tree | d04aab6b335e35380abf9d67702cdd2448d23da5 /llvm/lib/Target/Alpha | |
parent | cf9b1f6524436866cf5f8639193ebe89d92ae6b0 (diff) | |
download | bcm5719-llvm-f2641e1bc11b28db5722f7f6adec2ac416dd0f6c.tar.gz bcm5719-llvm-f2641e1bc11b28db5722f7f6adec2ac416dd0f6c.zip |
Add codegen support for vector select (in the IR this means a select
with a vector condition); such selects become VSELECT codegen nodes.
This patch also removes VSETCC codegen nodes, unifying them with SETCC
nodes (codegen was actually often using SETCC for vector SETCC already).
This ensures that various DAG combiner optimizations kick in for vector
comparisons. Passes dragonegg bootstrap with no testsuite regressions
(nightly testsuite as well as "make check-all"). Patch mostly by
Nadav Rotem.
llvm-svn: 139159
Diffstat (limited to 'llvm/lib/Target/Alpha')
-rw-r--r-- | llvm/lib/Target/Alpha/AlphaISelLowering.cpp | 3 | ||||
-rw-r--r-- | llvm/lib/Target/Alpha/AlphaISelLowering.h | 2 |
2 files changed, 3 insertions, 2 deletions
diff --git a/llvm/lib/Target/Alpha/AlphaISelLowering.cpp b/llvm/lib/Target/Alpha/AlphaISelLowering.cpp index 68ae71530ac..3057eb8c57f 100644 --- a/llvm/lib/Target/Alpha/AlphaISelLowering.cpp +++ b/llvm/lib/Target/Alpha/AlphaISelLowering.cpp @@ -49,6 +49,7 @@ AlphaTargetLowering::AlphaTargetLowering(TargetMachine &TM) // Set up the TargetLowering object. //I am having problems with shr n i8 1 setBooleanContents(ZeroOrOneBooleanContent); + setBooleanVectorContents(ZeroOrOneBooleanContent); // FIXME: Is this correct? addRegisterClass(MVT::i64, Alpha::GPRCRegisterClass); addRegisterClass(MVT::f64, Alpha::F8RCRegisterClass); @@ -168,7 +169,7 @@ AlphaTargetLowering::AlphaTargetLowering(TargetMachine &TM) computeRegisterProperties(); } -MVT::SimpleValueType AlphaTargetLowering::getSetCCResultType(EVT VT) const { +EVT AlphaTargetLowering::getSetCCResultType(EVT VT) const { return MVT::i64; } diff --git a/llvm/lib/Target/Alpha/AlphaISelLowering.h b/llvm/lib/Target/Alpha/AlphaISelLowering.h index 13383f4430f..80f8efaea5d 100644 --- a/llvm/lib/Target/Alpha/AlphaISelLowering.h +++ b/llvm/lib/Target/Alpha/AlphaISelLowering.h @@ -66,7 +66,7 @@ namespace llvm { virtual MVT getShiftAmountTy(EVT LHSTy) const { return MVT::i64; } /// getSetCCResultType - Get the SETCC result ValueType - virtual MVT::SimpleValueType getSetCCResultType(EVT VT) const; + virtual EVT getSetCCResultType(EVT VT) const; /// LowerOperation - Provide custom lowering hooks for some operations. /// |