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authorEvan Cheng <evan.cheng@apple.com>2006-11-15 20:58:11 +0000
committerEvan Cheng <evan.cheng@apple.com>2006-11-15 20:58:11 +0000
commitdc2c8748a7dc0a622a672f118cc8648feb908698 (patch)
treed58bf0d5d29d338de93a516747b328c855228694 /llvm/lib/Target/Alpha
parentbbbcac39e6b1010a9c717acada97fea4adca0b5e (diff)
downloadbcm5719-llvm-dc2c8748a7dc0a622a672f118cc8648feb908698.tar.gz
bcm5719-llvm-dc2c8748a7dc0a622a672f118cc8648feb908698.zip
Properly transfer kill / dead info.
llvm-svn: 31765
Diffstat (limited to 'llvm/lib/Target/Alpha')
-rw-r--r--llvm/lib/Target/Alpha/AlphaRegisterInfo.cpp7
1 files changed, 5 insertions, 2 deletions
diff --git a/llvm/lib/Target/Alpha/AlphaRegisterInfo.cpp b/llvm/lib/Target/Alpha/AlphaRegisterInfo.cpp
index 6be5e074a39..b3efe056861 100644
--- a/llvm/lib/Target/Alpha/AlphaRegisterInfo.cpp
+++ b/llvm/lib/Target/Alpha/AlphaRegisterInfo.cpp
@@ -104,6 +104,7 @@ MachineInstr *AlphaRegisterInfo::foldMemoryOperand(MachineInstr *MI,
// Make sure this is a reg-reg copy.
unsigned Opc = MI->getOpcode();
+ MachineInstr *NewMI = NULL;
switch(Opc) {
default:
break;
@@ -115,18 +116,20 @@ MachineInstr *AlphaRegisterInfo::foldMemoryOperand(MachineInstr *MI,
unsigned InReg = MI->getOperand(1).getReg();
Opc = (Opc == Alpha::BISr) ? Alpha::STQ :
((Opc == Alpha::CPYSS) ? Alpha::STS : Alpha::STT);
- return BuildMI(TII, Opc, 3).addReg(InReg).addFrameIndex(FrameIndex)
+ NewMI = BuildMI(TII, Opc, 3).addReg(InReg).addFrameIndex(FrameIndex)
.addReg(Alpha::F31);
} else { // load -> move
unsigned OutReg = MI->getOperand(0).getReg();
Opc = (Opc == Alpha::BISr) ? Alpha::LDQ :
((Opc == Alpha::CPYSS) ? Alpha::LDS : Alpha::LDT);
- return BuildMI(TII, Opc, 2, OutReg).addFrameIndex(FrameIndex)
+ NewMI = BuildMI(TII, Opc, 2, OutReg).addFrameIndex(FrameIndex)
.addReg(Alpha::F31);
}
}
break;
}
+ if (NewMI)
+ NewMI->copyKillDeadInfo(MI);
return 0;
}
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