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| author | Tim Northover <tnorthover@apple.com> | 2014-07-17 10:51:23 +0000 |
|---|---|---|
| committer | Tim Northover <tnorthover@apple.com> | 2014-07-17 10:51:23 +0000 |
| commit | fd7e4249359f510d21c2b682176cdb28dfa4e7e4 (patch) | |
| tree | c6f154b34d59f3708bea28534939101fdc74b37d /llvm/lib/Target/ARM | |
| parent | 2355066e4303a8c948ee9c7b8e3f28d778eb2180 (diff) | |
| download | bcm5719-llvm-fd7e4249359f510d21c2b682176cdb28dfa4e7e4.tar.gz bcm5719-llvm-fd7e4249359f510d21c2b682176cdb28dfa4e7e4.zip | |
CodeGen: extend f16 conversions to permit types > float.
This makes the two intrinsics @llvm.convert.from.f16 and
@llvm.convert.to.f16 accept types other than simple "float". This is
only strictly needed for the truncate operation, since otherwise
double rounding occurs and there's no way to represent the strict IEEE
conversion. However, for symmetry we allow larger types in the extend
too.
During legalization, we can expand an "fp16_to_double" operation into
two extends for convenience, but abort when the truncate isn't legal. A new
libcall is probably needed here.
Even after this commit, various target tweaks are needed to actually use the
extended intrinsics. I've put these into separate commits for clarity, so there
are no actual tests of f64 conversion here.
llvm-svn: 213248
Diffstat (limited to 'llvm/lib/Target/ARM')
| -rw-r--r-- | llvm/lib/Target/ARM/ARMISelLowering.cpp | 4 | ||||
| -rw-r--r-- | llvm/lib/Target/ARM/ARMInstrVFP.td | 4 |
2 files changed, 4 insertions, 4 deletions
diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp index 4bfa5a8b5c6..e74d0540eb0 100644 --- a/llvm/lib/Target/ARM/ARMISelLowering.cpp +++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp @@ -827,8 +827,8 @@ ARMTargetLowering::ARMTargetLowering(TargetMachine &TM) } // Special handling for half-precision FP. if (!Subtarget->hasFP16()) { - setOperationAction(ISD::FP16_TO_FP32, MVT::f32, Expand); - setOperationAction(ISD::FP32_TO_FP16, MVT::i32, Expand); + setOperationAction(ISD::FP16_TO_FP, MVT::f32, Expand); + setOperationAction(ISD::FP_TO_FP16, MVT::f32, Expand); } } diff --git a/llvm/lib/Target/ARM/ARMInstrVFP.td b/llvm/lib/Target/ARM/ARMInstrVFP.td index 1d7802a2c7f..e709e59b3fa 100644 --- a/llvm/lib/Target/ARM/ARMInstrVFP.td +++ b/llvm/lib/Target/ARM/ARMInstrVFP.td @@ -551,10 +551,10 @@ def VCVTBSH: ASuI<0b11101, 0b11, 0b0011, 0b01, 0, (outs SPR:$Sd), (ins SPR:$Sm), /* FIXME */ IIC_fpCVTHS, "vcvtb", ".f16.f32\t$Sd, $Sm", [/* For disassembly only; pattern left blank */]>; -def : Pat<(f32_to_f16 SPR:$a), +def : Pat<(fp_to_f16 SPR:$a), (i32 (COPY_TO_REGCLASS (VCVTBSH SPR:$a), GPR))>; -def : Pat<(f16_to_f32 GPR:$a), +def : Pat<(f16_to_fp GPR:$a), (VCVTBHS (COPY_TO_REGCLASS GPR:$a, SPR))>; def VCVTTHS: ASuI<0b11101, 0b11, 0b0010, 0b11, 0, (outs SPR:$Sd), (ins SPR:$Sm), |
