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| author | Evan Cheng <evan.cheng@apple.com> | 2009-06-23 18:14:38 +0000 | 
|---|---|---|
| committer | Evan Cheng <evan.cheng@apple.com> | 2009-06-23 18:14:38 +0000 | 
| commit | e379107cdcbe5fc829db809747fa02d441f3a35d (patch) | |
| tree | 0ec18c5a8d948894600e07512ebf5730142f32b8 /llvm/lib/Target/ARM | |
| parent | bf45b3e2adc7eca8799f70a2c1cb001a4723cee7 (diff) | |
| download | bcm5719-llvm-e379107cdcbe5fc829db809747fa02d441f3a35d.tar.gz bcm5719-llvm-e379107cdcbe5fc829db809747fa02d441f3a35d.zip | |
Rename SelectShifterOperand to SelectThumb2ShifterOperandReg.
llvm-svn: 73975
Diffstat (limited to 'llvm/lib/Target/ARM')
| -rw-r--r-- | llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp | 12 | ||||
| -rw-r--r-- | llvm/lib/Target/ARM/ARMInstrThumb2.td | 2 | 
2 files changed, 7 insertions, 7 deletions
| diff --git a/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp b/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp index ee9dadff151..be543a91ef2 100644 --- a/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp +++ b/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp @@ -92,8 +92,8 @@ public:    bool SelectThumbAddrModeSP(SDValue Op, SDValue N, SDValue &Base,                               SDValue &OffImm); -  bool SelectShifterOperand(SDValue Op, SDValue N, -                            SDValue &BaseReg, SDValue &Opc); +  bool SelectThumb2ShifterOperandReg(SDValue Op, SDValue N, +                                     SDValue &BaseReg, SDValue &Opc);    bool SelectShifterOperandReg(SDValue Op, SDValue N, SDValue &A,                                 SDValue &B, SDValue &C); @@ -520,10 +520,10 @@ bool ARMDAGToDAGISel::SelectThumbAddrModeSP(SDValue Op, SDValue N,    return false;  } -bool ARMDAGToDAGISel::SelectShifterOperand(SDValue Op, -                                           SDValue N, -                                           SDValue &BaseReg, -                                           SDValue &Opc) { +bool ARMDAGToDAGISel::SelectThumb2ShifterOperandReg(SDValue Op, +                                                    SDValue N, +                                                    SDValue &BaseReg, +                                                    SDValue &Opc) {    ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N);    // Don't match base register only case. That is matched to a separate diff --git a/llvm/lib/Target/ARM/ARMInstrThumb2.td b/llvm/lib/Target/ARM/ARMInstrThumb2.td index 9790c2bdee6..e0617e46620 100644 --- a/llvm/lib/Target/ARM/ARMInstrThumb2.td +++ b/llvm/lib/Target/ARM/ARMInstrThumb2.td @@ -14,7 +14,7 @@  // Shifted operands. No register controlled shifts for Thumb2.  // Note: We do not support rrx shifted operands yet.  def t2_so_reg : Operand<i32>,    // reg imm -                ComplexPattern<i32, 2, "SelectShifterOperand", +                ComplexPattern<i32, 2, "SelectThumb2ShifterOperandReg",                                 [shl,srl,sra,rotr]> {    let PrintMethod = "printSOOperand";    let MIOperandInfo = (ops GPR, i32imm); | 

