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authorOleg Ranevskyy <oranevskyy@accesssoftek.com>2016-12-01 22:58:35 +0000
committerOleg Ranevskyy <oranevskyy@accesssoftek.com>2016-12-01 22:58:35 +0000
commite2ae41519f162b901860585a6bfb98295ff2e846 (patch)
tree1e41d1c28914f7df78b3c1ce26149c703cfba6d4 /llvm/lib/Target/ARM
parent704395a25a409e21d517572080602d21c3b6fed8 (diff)
downloadbcm5719-llvm-e2ae41519f162b901860585a6bfb98295ff2e846.tar.gz
bcm5719-llvm-e2ae41519f162b901860585a6bfb98295ff2e846.zip
[ARM] Fix for 64-bit CAS expansion on ARM32 with -O0
Summary: This patch fixes comparison of 64-bit atomic with its expected value in CMP_SWAP_64 expansion. Currently, the low words are compared with CMP, while the high words are compared with SBC. SBC expects the carry flag to be set if CMP detects a difference. CMP might leave the carry unset for unequal arguments though if the first one is >= than the second. This might cause the comparison logic to detect false equality. Example of the broken C++ code: ``` std::atomic<long long> at(2); long long ll = 1; std::atomic_compare_exchange_strong(&at, &ll, 3); ``` Even though the atomic `at` and the expected value `ll` are not equal and `atomic_compare_exchange_strong` returns `false`, `at` is changed to 3. The patch replaces SBC with CMPEQ. Reviewers: t.p.northover Subscribers: aemerson, rengolin, llvm-commits, asl Differential Revision: https://reviews.llvm.org/D27315 llvm-svn: 288433
Diffstat (limited to 'llvm/lib/Target/ARM')
-rw-r--r--llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp11
1 files changed, 4 insertions, 7 deletions
diff --git a/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp b/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
index e2c386348ed..95fcc8dcb45 100644
--- a/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
+++ b/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
@@ -935,13 +935,10 @@ bool ARMExpandPseudo::ExpandCMP_SWAP_64(MachineBasicBlock &MBB,
.addReg(DestLo, getKillRegState(Dest.isDead()))
.addReg(DesiredLo, getKillRegState(Desired.isDead())));
- unsigned SBCrr = IsThumb ? ARM::t2SBCrr : ARM::SBCrr;
- MIB = BuildMI(LoadCmpBB, DL, TII->get(SBCrr))
- .addReg(StatusReg, RegState::Define | RegState::Dead)
- .addReg(DestHi, getKillRegState(Dest.isDead()))
- .addReg(DesiredHi, getKillRegState(Desired.isDead()));
- AddDefaultPred(MIB);
- MIB.addReg(ARM::CPSR, RegState::Kill);
+ BuildMI(LoadCmpBB, DL, TII->get(CMPrr))
+ .addReg(DestHi, getKillRegState(Dest.isDead()))
+ .addReg(DesiredHi, getKillRegState(Desired.isDead()))
+ .addImm(ARMCC::EQ).addReg(ARM::CPSR, RegState::Kill);
unsigned Bcc = IsThumb ? ARM::tBcc : ARM::Bcc;
BuildMI(LoadCmpBB, DL, TII->get(Bcc))
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