PredicateInstruction returns true if the operation was successful.

llvm-svn: 37124

2 files changed, 8 insertions, 4 deletions

diff --git a/llvm/lib/Target/ARM/ARMInstrInfo.cpp b/llvm/lib/Target/ARM/ARMInstrInfo.cpp
index b631124b6eb..891ae558f3d 100644
--- a/llvm/lib/Target/ARM/ARMInstrInfo.cpp
+++ b/llvm/lib/Target/ARM/ARMInstrInfo.cpp
@@ -423,17 +423,21 @@ ReverseBranchCondition(std::vector<MachineOperand> &Cond) const {
   return false;
 }
 
-void ARMInstrInfo::PredicateInstruction(MachineInstr *MI,
+bool ARMInstrInfo::PredicateInstruction(MachineInstr *MI,
                                       std::vector<MachineOperand> &Cond) const {
   unsigned Opc = MI->getOpcode();
   if (Opc == ARM::B || Opc == ARM::tB) {
     MI->setInstrDescriptor(get(Opc == ARM::B ? ARM::Bcc : ARM::tBcc));
     MI->addImmOperand(Cond[0].getImmedValue());
-    return;
+    return true;
   }
 
   MachineOperand *PMO = MI->findFirstPredOperand();
-  PMO->setImm(Cond[0].getImmedValue());
+  if (PMO) {
+    PMO->setImm(Cond[0].getImmedValue());
+    return true;
+  }
+  return false;
 }
 
 
diff --git a/llvm/lib/Target/ARM/ARMInstrInfo.h b/llvm/lib/Target/ARM/ARMInstrInfo.h
index cb0b812e161..33645b2d334 100644
--- a/llvm/lib/Target/ARM/ARMInstrInfo.h
+++ b/llvm/lib/Target/ARM/ARMInstrInfo.h
@@ -104,7 +104,7 @@ public:
   virtual bool ReverseBranchCondition(std::vector<MachineOperand> &Cond) const;
 
   // Predication support.
-  virtual void PredicateInstruction(MachineInstr *MI,
+  virtual bool PredicateInstruction(MachineInstr *MI,
                                     std::vector<MachineOperand> &Cond) const;
 };