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authorJohnny Chen <johnny.chen@apple.com>2011-04-11 23:33:30 +0000
committerJohnny Chen <johnny.chen@apple.com>2011-04-11 23:33:30 +0000
commitdc8bf9ec08641477675c9d85cf9fcaa9c31487d5 (patch)
treecb55aaed5358148a1e5333de49099c22593f0c7f /llvm/lib/Target/ARM
parent7d4cdae5643413120e19a7de2b6db7b83d1a6b26 (diff)
downloadbcm5719-llvm-dc8bf9ec08641477675c9d85cf9fcaa9c31487d5.tar.gz
bcm5719-llvm-dc8bf9ec08641477675c9d85cf9fcaa9c31487d5.zip
Thumb disassembler was erroneously rejecting "blx sp" instruction.
rdar://problem/9267838 llvm-svn: 129320
Diffstat (limited to 'llvm/lib/Target/ARM')
-rw-r--r--llvm/lib/Target/ARM/ARMInstrThumb.td9
-rw-r--r--llvm/lib/Target/ARM/Disassembler/ThumbDisassemblerCore.h7
2 files changed, 14 insertions, 2 deletions
diff --git a/llvm/lib/Target/ARM/ARMInstrThumb.td b/llvm/lib/Target/ARM/ARMInstrThumb.td
index 15ab4557dea..e3a9742bc76 100644
--- a/llvm/lib/Target/ARM/ARMInstrThumb.td
+++ b/llvm/lib/Target/ARM/ARMInstrThumb.td
@@ -369,6 +369,15 @@ let isReturn = 1, isTerminator = 1, isBarrier = 1 in {
let Inst{2-0} = 0b000;
}
+ def tBX_Rm : TI<(outs), (ins pred:$p, GPR:$Rm), IIC_Br, "bx${p}\t$Rm",
+ [/* for disassembly only */]>,
+ T1Special<{1,1,0,?}> {
+ // A6.2.3 & A8.6.25
+ bits<4> Rm;
+ let Inst{6-3} = Rm;
+ let Inst{2-0} = 0b000;
+ }
+
// Alternative return instruction used by vararg functions.
def tBX_RET_vararg : TI<(outs), (ins tGPR:$Rm),
IIC_Br, "bx\t$Rm",
diff --git a/llvm/lib/Target/ARM/Disassembler/ThumbDisassemblerCore.h b/llvm/lib/Target/ARM/Disassembler/ThumbDisassemblerCore.h
index 727fc1332ad..85816e02fef 100644
--- a/llvm/lib/Target/ARM/Disassembler/ThumbDisassemblerCore.h
+++ b/llvm/lib/Target/ARM/Disassembler/ThumbDisassemblerCore.h
@@ -485,10 +485,13 @@ static bool DisassembleThumb1Special(MCInst &MI, unsigned Opcode, uint32_t insn,
return true;
// BX/BLX has 1 reg operand: Rm.
- if (NumOps == 1) {
+ if (Opcode == ARM::tBLXr_r9 || Opcode == ARM::tBX_Rm) {
+ // Handling the two predicate operands before the reg operand.
+ if (!B->DoPredicateOperands(MI, Opcode, insn, NumOps))
+ return false;
MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
getT1Rm(insn))));
- NumOpsAdded = 1;
+ NumOpsAdded = 3;
return true;
}
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