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authorOliver Stannard <oliver.stannard@arm.com>2017-11-21 15:06:01 +0000
committerOliver Stannard <oliver.stannard@arm.com>2017-11-21 15:06:01 +0000
commitd6ca9879bab19410cbfc8c41d4c4b7a8f3668699 (patch)
tree387e236321f4d535880b571c98eae82c10fab7ca /llvm/lib/Target/ARM
parent1b7f8d5b043a2c97d4db17fdbd092cf097d8445d (diff)
downloadbcm5719-llvm-d6ca9879bab19410cbfc8c41d4c4b7a8f3668699.tar.gz
bcm5719-llvm-d6ca9879bab19410cbfc8c41d4c4b7a8f3668699.zip
[ARM] Add diagnostics for SPR/DPR lists
Differential revision: https://reviews.llvm.org/D39195 llvm-svn: 318766
Diffstat (limited to 'llvm/lib/Target/ARM')
-rw-r--r--llvm/lib/Target/ARM/ARMInstrInfo.td10
-rw-r--r--llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp3
2 files changed, 11 insertions, 2 deletions
diff --git a/llvm/lib/Target/ARM/ARMInstrInfo.td b/llvm/lib/Target/ARM/ARMInstrInfo.td
index 37a8594e544..4e13af59630 100644
--- a/llvm/lib/Target/ARM/ARMInstrInfo.td
+++ b/llvm/lib/Target/ARM/ARMInstrInfo.td
@@ -526,7 +526,10 @@ def reglist : Operand<i32> {
def GPRPairOp : RegisterOperand<GPRPair, "printGPRPairOperand">;
-def DPRRegListAsmOperand : AsmOperandClass { let Name = "DPRRegList"; }
+def DPRRegListAsmOperand : AsmOperandClass {
+ let Name = "DPRRegList";
+ let DiagnosticType = "DPR_RegList";
+}
def dpr_reglist : Operand<i32> {
let EncoderMethod = "getRegisterListOpValue";
let ParserMatchClass = DPRRegListAsmOperand;
@@ -534,7 +537,10 @@ def dpr_reglist : Operand<i32> {
let DecoderMethod = "DecodeDPRRegListOperand";
}
-def SPRRegListAsmOperand : AsmOperandClass { let Name = "SPRRegList"; }
+def SPRRegListAsmOperand : AsmOperandClass {
+ let Name = "SPRRegList";
+ let DiagnosticString = "operand must be a list of registers in range [s0, s31]";
+}
def spr_reglist : Operand<i32> {
let EncoderMethod = "getRegisterListOpValue";
let ParserMatchClass = SPRRegListAsmOperand;
diff --git a/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp b/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
index caa46bcb98d..1d59cd1a745 100644
--- a/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
+++ b/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
@@ -10137,6 +10137,9 @@ ARMAsmParser::getCustomOperandDiag(ARMMatchResultTy MatchError) {
case Match_DPR:
return hasD16() ? "operand must be a register in range [d0, d15]"
: "operand must be a register in range [d0, d31]";
+ case Match_DPR_RegList:
+ return hasD16() ? "operand must be a list of registers in range [d0, d15]"
+ : "operand must be a list of registers in range [d0, d31]";
// For all other diags, use the static string from tablegen.
default:
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