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| author | Renato Golin <renato.golin@linaro.org> | 2017-05-16 17:59:07 +0000 |
|---|---|---|
| committer | Renato Golin <renato.golin@linaro.org> | 2017-05-16 17:59:07 +0000 |
| commit | d69570e0171c8bb14ffb6ce0de3eba289ee0794b (patch) | |
| tree | b2459fbe54a066779725fd76f6b3753882c53e12 /llvm/lib/Target/ARM | |
| parent | d2b8aaa05a7fa1eef696b5e43db3a535a63559ec (diff) | |
| download | bcm5719-llvm-d69570e0171c8bb14ffb6ce0de3eba289ee0794b.tar.gz bcm5719-llvm-d69570e0171c8bb14ffb6ce0de3eba289ee0794b.zip | |
Revert "[ARM] Mark LEApcrel instructions as isAsCheapAsAMove"
Revert "[ARM] Mark LEApcrel as not having side effects"
This reverts commit r303054 and r303053, as they broke the ARM
self-hosting buildbots:
http://lab.llvm.org:8011/builders/clang-cmake-thumbv7-a15-full-sh/builds/1550
http://lab.llvm.org:8011/builders/clang-cmake-armv7-a15-selfhost-neon/builds/1349
http://lab.llvm.org:8011/builders/clang-cmake-armv7-a15-selfhost/builds/1845
Offline investigation on course.
llvm-svn: 303193
Diffstat (limited to 'llvm/lib/Target/ARM')
| -rw-r--r-- | llvm/lib/Target/ARM/ARMInstrInfo.td | 4 | ||||
| -rw-r--r-- | llvm/lib/Target/ARM/ARMInstrThumb.td | 2 | ||||
| -rw-r--r-- | llvm/lib/Target/ARM/ARMInstrThumb2.td | 2 |
3 files changed, 4 insertions, 4 deletions
diff --git a/llvm/lib/Target/ARM/ARMInstrInfo.td b/llvm/lib/Target/ARM/ARMInstrInfo.td index 5b7666af876..d06b7d0896f 100644 --- a/llvm/lib/Target/ARM/ARMInstrInfo.td +++ b/llvm/lib/Target/ARM/ARMInstrInfo.td @@ -2222,14 +2222,14 @@ def ADR : AI1<{0,?,?,0}, (outs GPR:$Rd), (ins adrlabel:$label), let Inst{11-0} = label{11-0}; } -let hasSideEffects = 0, isReMaterializable = 1, isAsCheapAsAMove = 1 in +let hasSideEffects = 1 in { def LEApcrel : ARMPseudoInst<(outs GPR:$Rd), (ins i32imm:$label, pred:$p), 4, IIC_iALUi, []>, Sched<[WriteALU, ReadALU]>; -let hasSideEffects = 1 in def LEApcrelJT : ARMPseudoInst<(outs GPR:$Rd), (ins i32imm:$label, pred:$p), 4, IIC_iALUi, []>, Sched<[WriteALU, ReadALU]>; +} //===----------------------------------------------------------------------===// // Control Flow Instructions. diff --git a/llvm/lib/Target/ARM/ARMInstrThumb.td b/llvm/lib/Target/ARM/ARMInstrThumb.td index 118627fd5d7..bee83dfb6f6 100644 --- a/llvm/lib/Target/ARM/ARMInstrThumb.td +++ b/llvm/lib/Target/ARM/ARMInstrThumb.td @@ -1402,7 +1402,7 @@ def tADR : T1I<(outs tGPR:$Rd), (ins t_adrlabel:$addr, pred:$p), let DecoderMethod = "DecodeThumbAddSpecialReg"; } -let hasSideEffects = 0, isReMaterializable = 1, isAsCheapAsAMove = 1 in +let hasSideEffects = 0, isReMaterializable = 1 in def tLEApcrel : tPseudoInst<(outs tGPR:$Rd), (ins i32imm:$label, pred:$p), 2, IIC_iALUi, []>, Sched<[WriteALU]>; diff --git a/llvm/lib/Target/ARM/ARMInstrThumb2.td b/llvm/lib/Target/ARM/ARMInstrThumb2.td index 842c46cc2b6..bf3d820e7b7 100644 --- a/llvm/lib/Target/ARM/ARMInstrThumb2.td +++ b/llvm/lib/Target/ARM/ARMInstrThumb2.td @@ -1227,7 +1227,7 @@ def t2ADR : T2PCOneRegImm<(outs rGPR:$Rd), let DecoderMethod = "DecodeT2Adr"; } -let hasSideEffects = 0, isReMaterializable = 1, isAsCheapAsAMove = 1 in +let hasSideEffects = 0, isReMaterializable = 1 in def t2LEApcrel : t2PseudoInst<(outs rGPR:$Rd), (ins i32imm:$label, pred:$p), 4, IIC_iALUi, []>, Sched<[WriteALU, ReadALU]>; let hasSideEffects = 1 in |
