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| author | Andre Vieira <andre.simoesdiasvieira@arm.com> | 2017-10-18 14:47:37 +0000 |
|---|---|---|
| committer | Andre Vieira <andre.simoesdiasvieira@arm.com> | 2017-10-18 14:47:37 +0000 |
| commit | d4a25707f007db1536035a91ed39f13ab6ba35c2 (patch) | |
| tree | 98849280bcb4a9234b431cdd14589556e09f067b /llvm/lib/Target/ARM | |
| parent | 03c2c65b2d288b936f5b298473314d665c89ef45 (diff) | |
| download | bcm5719-llvm-d4a25707f007db1536035a91ed39f13ab6ba35c2.tar.gz bcm5719-llvm-d4a25707f007db1536035a91ed39f13ab6ba35c2.zip | |
[ARM] Fix disassembly for conditional VMRS and VMSR instructions in ARM mode
Differential Revision: https://reviews.llvm.org/D38347
llvm-svn: 316085
Diffstat (limited to 'llvm/lib/Target/ARM')
| -rw-r--r-- | llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp | 10 |
1 files changed, 8 insertions, 2 deletions
diff --git a/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp b/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp index 737450d6b34..a29a2eeccfe 100644 --- a/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp +++ b/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp @@ -5340,8 +5340,14 @@ static DecodeStatus DecodeForVMRSandVMSR(MCInst &Inst, unsigned Val, } else Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)); - Inst.addOperand(MCOperand::createImm(ARMCC::AL)); - Inst.addOperand(MCOperand::createReg(0)); + if (featureBits[ARM::ModeThumb]) { + Inst.addOperand(MCOperand::createImm(ARMCC::AL)); + Inst.addOperand(MCOperand::createReg(0)); + } else { + unsigned pred = fieldFromInstruction(Val, 28, 4); + if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) + return MCDisassembler::Fail; + } return S; } |
