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authorBob Wilson <bob.wilson@apple.com>2010-04-14 20:45:23 +0000
committerBob Wilson <bob.wilson@apple.com>2010-04-14 20:45:23 +0000
commitc05b887c84f80d8661cf37b5efee1763ead0add9 (patch)
tree9812d0316765f0f239b8a0adad2b475133f1254d /llvm/lib/Target/ARM
parentdd6697b4fa8261c6f0a0da22b164f909d4fdf2db (diff)
downloadbcm5719-llvm-c05b887c84f80d8661cf37b5efee1763ead0add9.tar.gz
bcm5719-llvm-c05b887c84f80d8661cf37b5efee1763ead0add9.zip
Don't custom lower bit converts to ARM VMOVDRRD or VMOVDRR when the operand
does not have a legal type. The legalizer does not know how to handle those nodes. Radar 7854640. llvm-svn: 101282
Diffstat (limited to 'llvm/lib/Target/ARM')
-rw-r--r--llvm/lib/Target/ARM/ARMISelLowering.cpp25
1 files changed, 16 insertions, 9 deletions
diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp
index cd0268d9f2d..dee3150fee3 100644
--- a/llvm/lib/Target/ARM/ARMISelLowering.cpp
+++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp
@@ -2167,6 +2167,13 @@ ARMTargetLowering::EmitTargetCodeForMemcpy(SelectionDAG &DAG, DebugLoc dl,
static SDValue ExpandBIT_CONVERT(SDNode *N, SelectionDAG &DAG) {
SDValue Op = N->getOperand(0);
+
+ // Do not create a VMOVDRR or VMOVRRD node if the operand type is not
+ // legal. The legalizer won't know what to do with that.
+ const TargetLowering &TLI = DAG.getTargetLoweringInfo();
+ if (!TLI.isTypeLegal(Op.getValueType()))
+ return SDValue();
+
DebugLoc dl = N->getDebugLoc();
if (N->getValueType(0) == MVT::f64) {
// Turn i64->f64 into VMOVDRR.
@@ -3114,21 +3121,21 @@ SDValue ARMTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) {
void ARMTargetLowering::ReplaceNodeResults(SDNode *N,
SmallVectorImpl<SDValue>&Results,
SelectionDAG &DAG) {
+ SDValue Res;
switch (N->getOpcode()) {
default:
llvm_unreachable("Don't know how to custom expand this!");
- return;
+ break;
case ISD::BIT_CONVERT:
- Results.push_back(ExpandBIT_CONVERT(N, DAG));
- return;
+ Res = ExpandBIT_CONVERT(N, DAG);
+ break;
case ISD::SRL:
- case ISD::SRA: {
- SDValue Res = LowerShift(N, DAG, Subtarget);
- if (Res.getNode())
- Results.push_back(Res);
- return;
- }
+ case ISD::SRA:
+ Res = LowerShift(N, DAG, Subtarget);
+ break;
}
+ if (Res.getNode())
+ Results.push_back(Res);
}
//===----------------------------------------------------------------------===//
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