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authorRafael Espindola <rafael.espindola@gmail.com>2006-09-11 19:23:32 +0000
committerRafael Espindola <rafael.espindola@gmail.com>2006-09-11 19:23:32 +0000
commitbccf9c2f1bbbcc5eab2720820f26d37c67529991 (patch)
tree1e93e330cccc2e243d75e9992ea427a76dc8663e /llvm/lib/Target/ARM
parentf37b4ee4c2f14502a1cab8726d95d2d6890e9b4d (diff)
downloadbcm5719-llvm-bccf9c2f1bbbcc5eab2720820f26d37c67529991.tar.gz
bcm5719-llvm-bccf9c2f1bbbcc5eab2720820f26d37c67529991.zip
add the correct fallback for ARMDAGToDAGISel::SelectAddrMode1
llvm-svn: 30261
Diffstat (limited to 'llvm/lib/Target/ARM')
-rw-r--r--llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp9
1 files changed, 3 insertions, 6 deletions
diff --git a/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp b/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
index 353e3fccf4a..c356f09a691 100644
--- a/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
+++ b/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
@@ -482,19 +482,16 @@ static bool isInt12Immediate(SDOperand Op, short &Imm) {
bool ARMDAGToDAGISel::SelectAddrMode1(SDOperand N,
SDOperand &Arg) {
switch(N.getOpcode()) {
- case ISD::CopyFromReg:
- Arg = N;
- return true;
case ISD::Constant: {
//TODO:check that we have a valid constant
int32_t t = cast<ConstantSDNode>(N)->getValue();
Arg = CurDAG->getTargetConstant(t, MVT::i32);
return true;
}
- default:
- std::cerr << "OpCode = " << N.getOpcode() << "\n";
- assert(0);
}
+
+ Arg = N;
+ return true;
}
//register plus/minus 12 bit offset
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