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| author | Nadav Rotem <nrotem@apple.com> | 2013-01-09 22:29:00 +0000 |
|---|---|---|
| committer | Nadav Rotem <nrotem@apple.com> | 2013-01-09 22:29:00 +0000 |
| commit | b1791a75cd2f41a3d8fb473f7d180979e5a15128 (patch) | |
| tree | 6b8368042c1224f60b5fb8e3d6e625d4721ea30b /llvm/lib/Target/ARM | |
| parent | dd7d8a0f358c4a8fa88d42f029d2be31426f4fbb (diff) | |
| download | bcm5719-llvm-b1791a75cd2f41a3d8fb473f7d180979e5a15128.tar.gz bcm5719-llvm-b1791a75cd2f41a3d8fb473f7d180979e5a15128.zip | |
ARM Cost model: Use the size of vector registers and widest vectorizable instruction to determine the max vectorization factor.
llvm-svn: 172010
Diffstat (limited to 'llvm/lib/Target/ARM')
| -rw-r--r-- | llvm/lib/Target/ARM/ARMTargetTransformInfo.cpp | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/llvm/lib/Target/ARM/ARMTargetTransformInfo.cpp b/llvm/lib/Target/ARM/ARMTargetTransformInfo.cpp index 634004acb45..404a6fff117 100644 --- a/llvm/lib/Target/ARM/ARMTargetTransformInfo.cpp +++ b/llvm/lib/Target/ARM/ARMTargetTransformInfo.cpp @@ -94,6 +94,16 @@ public: return 16; } + unsigned getRegisterBitWidth(bool Vector) const { + if (Vector) { + if (ST->hasNEON()) + return 128; + return 0; + } + + return 32; + } + unsigned getMaximumUnrollFactor() const { // These are out of order CPUs: if (ST->isCortexA15() || ST->isSwift()) |
