diff options
| author | Sanjay Patel <spatel@rotateright.com> | 2017-02-27 21:30:54 +0000 |
|---|---|---|
| committer | Sanjay Patel <spatel@rotateright.com> | 2017-02-27 21:30:54 +0000 |
| commit | ae7873fe551b4bd0cfc24f86f9d82fb688e96297 (patch) | |
| tree | 2e2b44bc002d1c0ee7053e6784b4b2a0eefc88c7 /llvm/lib/Target/ARM | |
| parent | b7acfc0139bba6f5fdc3f4c409411f03dce543ab (diff) | |
| download | bcm5719-llvm-ae7873fe551b4bd0cfc24f86f9d82fb688e96297.tar.gz bcm5719-llvm-ae7873fe551b4bd0cfc24f86f9d82fb688e96297.zip | |
[ARM] don't transform an add(ext Cond), C to select unless there's a setcc of the condition
The transform in question claims to be doing:
// fold (add (select cc, 0, c), x) -> (select cc, x, (add, x, c))
...starting in PerformADDCombineWithOperands(), but it wasn't actually checking for a setcc node
for the sext/zext patterns.
This is exactly the opposite of a transform I'd like to add to DAGCombiner's foldSelectOfConstants(),
so I was seeing infinite loops with my draft of a patch applied.
The changes in select_const.ll look positive (less instructions). The change in arm-and-tst-peephole.ll
is unrelated. We're changing the input IR in that test to preserve the intent of the test, but that's
not affected by this code change.
Differential Revision:
https://reviews.llvm.org/D30355
llvm-svn: 296389
Diffstat (limited to 'llvm/lib/Target/ARM')
| -rw-r--r-- | llvm/lib/Target/ARM/ARMISelLowering.cpp | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp index ccebf465fc5..76df9a57015 100644 --- a/llvm/lib/Target/ARM/ARMISelLowering.cpp +++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp @@ -9163,7 +9163,7 @@ static bool isConditionalZeroOrAllOnes(SDNode *N, bool AllOnes, SDLoc dl(N); EVT VT = N->getValueType(0); CC = N->getOperand(0); - if (CC.getValueType() != MVT::i1) + if (CC.getValueType() != MVT::i1 || CC.getOpcode() != ISD::SETCC) return false; Invert = !AllOnes; if (AllOnes) |
